From patchwork Mon Aug 21 19:29:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9913561 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6B1F3600C8 for ; Mon, 21 Aug 2017 19:29:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C608287D7 for ; Mon, 21 Aug 2017 19:29:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5117C287E3; Mon, 21 Aug 2017 19:29:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D91FD287D7 for ; Mon, 21 Aug 2017 19:29:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754167AbdHUT3o (ORCPT ); Mon, 21 Aug 2017 15:29:44 -0400 Received: from mail-wr0-f174.google.com ([209.85.128.174]:38779 "EHLO mail-wr0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754030AbdHUT3n (ORCPT ); Mon, 21 Aug 2017 15:29:43 -0400 Received: by mail-wr0-f174.google.com with SMTP id p8so43218764wrf.5 for ; Mon, 21 Aug 2017 12:29:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lt5Vc3jPFYX7xUzjTmciGyhW5aRa2RkJ69BPzFtj69g=; b=ODphtQD+cRvTjx0j24WvYiSnxQSJR2cSasMheGYsB/B9tKO6q8QFlnqzoastBVsIHH tTUB4/v8EiVa+09n5/tVdMxY1R0ebjnk33lpYtM8iQkLJGvAAD/6lGDffNLxpaIYE3+E +EKZhAN3SJZpf+L9hPtRkVO0liyw04ZOSFuMc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lt5Vc3jPFYX7xUzjTmciGyhW5aRa2RkJ69BPzFtj69g=; b=K+Ybz/9QfaugcjEzMXMFz/p+G3c/aixgzSHZZyXDqb5EWsZZI/JOw90C+Mlwg34Rnc QjMnDHfb6+HbNfQneYzbeMSWhBzfJvKkn/PZIn15Sy1micxuQQ/pzS70ZlKz+BMhNccL RbE5mjkQIL9DF8Smzz/D+Y+iAVXd7iUQ11WDTd4Tp08WQdhK9S71Ew/4e+pWpeuy8GGO Ckjs4UYUmic7G9fohpZRryx+rdY87ctHywgK+MiTS5u27MPDdp0X6uzdxpjXfx/JYpMU kTx2MmFvqNpZXC+wzhc4rV9lOli8Y1kwgIDxDAlaNgZzCU5QLSxcZii+EcQf8bSsKPhQ qY8Q== X-Gm-Message-State: AHYfb5iWi52WDs230QDfij951WPEs6HNSvMVnHnR/OkJC/eUp2ntOwNi Mm8Am3xZwBqQn3/mBWwoQA== X-Received: by 10.223.196.10 with SMTP id v10mr807648wrf.5.1503343781907; Mon, 21 Aug 2017 12:29:41 -0700 (PDT) Received: from localhost.localdomain ([154.146.161.128]) by smtp.gmail.com with ESMTPSA id 2sm8998556wrp.63.2017.08.21.12.29.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 12:29:41 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Jingoo Han , Joao Pinto , Marc Zyngier , Rob Herring Subject: [PATCH 3/3] dt-bindings: designware: add binding for Designware PCIe in ECAM mode Date: Mon, 21 Aug 2017 20:29:07 +0100 Message-Id: <20170821192907.8695-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170821192907.8695-1-ard.biesheuvel@linaro.org> References: <20170821192907.8695-1-ard.biesheuvel@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Describe the binding for firmware-configured instances of the Synopsys Designware PCIe controller in RC mode. Cc: Rob Herring Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt new file mode 100644 index 000000000000..b8127b19c220 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt @@ -0,0 +1,56 @@ +* Synopsys Designware PCIe root complex in ECAM mode + +In some cases, firmware may already have configured the Synopsys Designware +PCIe controller in RC mode with static ATU window mappings that cover all +config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. +In this case, there is no need for the OS to perform any low level setup +of clocks or device registers, nor is there any reason for the driver to +reconfigure ATU windows for config and/or IO space accesses at runtime. + +Such hardware configurations should be described as "pci-host-ecam-generic" +if they are truly ECAM compatible. Configurations that require no low-level +setup by the OS nor any ATU window reconfiguration at runtime, but do +require special handling for type 0 config TLPs may instead be described as +"snps,dw-pcie-ecam". + +Required properties: +- compatible: should contain "snps,dw-pcie-ecam". + +Please refer to the binding document of "pci-host-ecam-generic" in the +file host-generic-pci.txt for a description of the remaining required +and optional properties. + + +* MSI support for Synopsys Designware PCIe root complex in ECAM mode + +Platforms that elect to perform all configuration of the RC in firmware +and use the "pci-host-ecam-generic" or "snps,dw-pcie-ecam" binding to +describe it to the OS may include a separate description of the embedded +MSI controller in case no MSI support is available in the core interrupt +controller. + +Required properties: +- compatible: should contain "snps,dw-pcie-msi". +- reg: a single region describing the device registers. +- interrupts: interrupt specifier for the interrupt that is asserted when + an MSI is received by the RC. +- msi-controller: empty property identifying this device as an MSI controller. + +Example for an implementation that routes all legacy INTx interrupts via SPI +#188 and all MSI interrupts via SPI #190: + + pcie@20000000 { + compatible = "snps,dw-pcie-ecam"; + device_type = "pci"; + msi-parent = <&msi0>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + ... + }; + + msi0: msi@10000000 { + compatible = "snps,dw-pcie-msi"; + reg = <0x0 0x10000000 0x0 0x10000>; + interrupts = ; + msi-controller; + };