From patchwork Thu Aug 24 18:43:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9920683 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6995360353 for ; Thu, 24 Aug 2017 18:43:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60DCC28C62 for ; Thu, 24 Aug 2017 18:43:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 55CEA28C54; Thu, 24 Aug 2017 18:43:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ADFD528C49 for ; Thu, 24 Aug 2017 18:43:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753487AbdHXSns (ORCPT ); Thu, 24 Aug 2017 14:43:48 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:38455 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752909AbdHXSnr (ORCPT ); Thu, 24 Aug 2017 14:43:47 -0400 Received: by mail-wm0-f44.google.com with SMTP id z132so1890329wmg.1 for ; Thu, 24 Aug 2017 11:43:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KcAKcfbpFiO6tiD5Qy9ZWKIIncTJyNDgD121kGXkCNs=; b=MskgJGpE4UGJW01b+PBKASJA63+RA3dh8AOqOkXe6T+R69olgehziP15sX+B07tQhs tIx70djuEPnOp6Ei5AsgLkUKQhirAHsPiP9yVep2EZKmjQXwDlWxIJ2oJLwRAJvJb1N8 v9WyG99oj2R6GTIRM9By0nBswNI2NblYvIWE0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KcAKcfbpFiO6tiD5Qy9ZWKIIncTJyNDgD121kGXkCNs=; b=RkhutrW9SZhtLHfii8keraEKbuUt3yblbUmr9MBuhEXxeDlgHTEPkpypqS41FKkkXg k8Zl84880p4erZSOZwCSSaRHisWbD5lKWh8E1FGODCtxo3nqErZdbRs0XR0jo5BxG1nA Hr1hzstNBVhm6hWd6Vwd3We/yJHHO/vyjRJXbEQYkX4DRFLvB16ODY0e9w3p8PzP/4Gs owmBX3tCouwNkP1no6cWBstuL1wILNb2MZdcItzAkUoYqWIOi4F9EStb2XmedpWjPUev CxPpWMZZ11RuH4gxPhYqCVWQXSFrnXRSOgOuzLqspZsWMe+BMa7MYGzmOxMwUd42Gz15 KAaQ== X-Gm-Message-State: AHYfb5ioYJPurr2a6y9KppDyaC4u1mxzbJKtYf/w17ifA5FStDD50TGS YFYyUePpsyLyn8849gLnHA== X-Received: by 10.28.29.75 with SMTP id d72mr69229wmd.152.1503600225788; Thu, 24 Aug 2017 11:43:45 -0700 (PDT) Received: from localhost.localdomain ([196.71.110.206]) by smtp.gmail.com with ESMTPSA id e2sm3531945wrd.60.2017.08.24.11.43.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Aug 2017 11:43:45 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: mw@semihalf.com, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Jingoo Han , Joao Pinto , Marc Zyngier Subject: [PATCH v2 1/3] pci: designware: add driver for DWC controller in ECAM shift mode Date: Thu, 24 Aug 2017 19:43:19 +0100 Message-Id: <20170824184321.19432-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170824184321.19432-1-ard.biesheuvel@linaro.org> References: <20170824184321.19432-1-ard.biesheuvel@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some implementations of the Synopsys Designware PCIe controller implement a so-called ECAM shift mode, which allows a static memory window to be configured that covers the configuration space of the entire bus range. If the firmware performs all the low level configuration that is required to expose this controller in a fully ECAM compatible manner, we can simply describe it as "pci-host-ecam-generic" and be done with it. However, it appears that in some cases (one of which is the Armada 80x0), the IP is synthesized with an ATU window size that does not allow the first bus to be mapped in a way that prevents the device on the downstream port from appearing more than once. So implement a driver that relies on the firmware to perform all low level initialization, and drives the controller in ECAM mode, but overrides the config space accessors to take the above quirk into account. Note that, unlike most drivers for this IP, this driver does not expose a fake bridge device at B/D/F 00:00.0. There is no point in doing so, given that this is not a true bridge, and does not require any windows to be configured in order for the downstream device to operate correctly. Omitting it also prevents the PCI resource allocation routines from handing out BAR space to it unnecessarily. Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Joao Pinto Signed-off-by: Ard Biesheuvel --- drivers/pci/dwc/Kconfig | 11 +++ drivers/pci/dwc/Makefile | 1 + drivers/pci/dwc/pcie-designware-ecam.c | 75 ++++++++++++++++++++ 3 files changed, 87 insertions(+) diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index d275aadc47ee..477576d07911 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -169,4 +169,15 @@ config PCIE_KIRIN Say Y here if you want PCIe controller support on HiSilicon Kirin series SoCs. +config PCIE_DW_HOST_ECAM + bool "Synopsys DesignWare PCIe controller in ECAM mode" + depends on OF && PCI + select PCI_HOST_COMMON + select IRQ_DOMAIN + help + Add support for Synopsys DesignWare PCIe controllers configured + by the firmware into ECAM shift mode. In some cases, these are + fully ECAM compliant, in which case the pci-host-generic driver + may be used instead. + endmenu diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile index c61be9738cce..7d5a23e5b767 100644 --- a/drivers/pci/dwc/Makefile +++ b/drivers/pci/dwc/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o +obj-$(CONFIG_PCIE_DW_HOST_ECAM) += pcie-designware-ecam.o obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),) diff --git a/drivers/pci/dwc/pcie-designware-ecam.c b/drivers/pci/dwc/pcie-designware-ecam.c new file mode 100644 index 000000000000..0f495bd2e33e --- /dev/null +++ b/drivers/pci/dwc/pcie-designware-ecam.c @@ -0,0 +1,75 @@ +/* + * Driver for mostly ECAM compatible Synopsys dw PCIe controllers + * configured by the firmware into RC mode + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (C) 2014 ARM Limited + * Copyright (C) 2017 Linaro Limited + * + * Authors: Will Deacon + * Ard Biesheuvel + */ + +#include +#include +#include +#include +#include +#include + +static int pci_dw_ecam_config_read(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pci_config_window *cfg = bus->sysdata; + + /* + * The Synopsys dw PCIe controller in RC mode will not filter type 0 + * config TLPs sent to devices 1 and up on its downstream port, + * resulting in devices appearing multiple times on bus 0 unless we + * filter them here. + */ + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + return pci_generic_config_read(bus, devfn, where, size, val); +} + +static int pci_dw_ecam_config_write(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) +{ + struct pci_config_window *cfg = bus->sysdata; + + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return pci_generic_config_write(bus, devfn, where, size, val); +} + +static struct pci_ecam_ops pci_dw_ecam_bus_ops = { + .pci_ops.map_bus = pci_ecam_map_bus, + .pci_ops.read = pci_dw_ecam_config_read, + .pci_ops.write = pci_dw_ecam_config_write, + .bus_shift = 20, +}; + +static const struct of_device_id pci_dw_ecam_of_match[] = { + { .compatible = "snps,dw-pcie-ecam" }, + { }, +}; + +static int pci_dw_ecam_probe(struct platform_device *pdev) +{ + return pci_host_common_probe(pdev, &pci_dw_ecam_bus_ops); +} + +static struct platform_driver pci_dw_ecam_driver = { + .driver.name = "pcie-designware-ecam", + .driver.of_match_table = pci_dw_ecam_of_match, + .driver.suppress_bind_attrs = true, + .probe = pci_dw_ecam_probe, +}; +builtin_platform_driver(pci_dw_ecam_driver);