From patchwork Thu Aug 24 18:43:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9920687 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 28064603FF for ; Thu, 24 Aug 2017 18:43:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1AAEC28C4C for ; Thu, 24 Aug 2017 18:43:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0D7B028C54; Thu, 24 Aug 2017 18:43:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7973928C5E for ; Thu, 24 Aug 2017 18:43:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752909AbdHXSnw (ORCPT ); Thu, 24 Aug 2017 14:43:52 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:35721 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753021AbdHXSnv (ORCPT ); Thu, 24 Aug 2017 14:43:51 -0400 Received: by mail-wm0-f50.google.com with SMTP id b189so2146954wmd.0 for ; Thu, 24 Aug 2017 11:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lt5Vc3jPFYX7xUzjTmciGyhW5aRa2RkJ69BPzFtj69g=; b=hUcVF6u3opREYgu+9N/xBPcFEwpdArsu5o/815B6kUZb5p8hNQNKwnY8dINnmwjzca SOG/Q4+KS78GnbXAjGLd7AXf5oElap0X1z7lW4z5ojeM3RIpG3BlIV/BzUKFdQfsSy2a AYHnDLp23ygdWJg0s012cEz1EAugkZIM6lpDU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lt5Vc3jPFYX7xUzjTmciGyhW5aRa2RkJ69BPzFtj69g=; b=lcFDW+o/76HixART7MYmkPjMO9U+76T6qUNWEQ0q9nV0GuleIl2317e2q/tnhs8cHS D6EV8tDzThS4Q82MDYMzelO+QsY+s7sUzg0vh3DAsrUX4wvmjEcch89YEq5CVRPUj1CO kkCUNrMYXwRHYkWiBetacswTEHRIbwQaGdZhG7J2nNdRCmX8AHet5ZBsbejgnDGeQbTy DvRHZkoGdgRAhMA//E4kP9Mh6YV10DF+fPA8mvq6WLmo8/BopziVsJ+MJxV/fG+lKoGP Q6yE1D2BFFt//NLnhJcbJsZ06JCnm7rjIm3E26LPtJEqhl3RbnYTO3xVrmZ58z3c0JFr HhXQ== X-Gm-Message-State: AHYfb5hXO2XjW1HF66YTmucjRIwXIrKEnlq3JWYx9cEiSia5cnKQ4l90 daeaP5jyIRFwd8AINuU0hw== X-Received: by 10.28.102.135 with SMTP id a129mr1716840wmc.44.1503600230289; Thu, 24 Aug 2017 11:43:50 -0700 (PDT) Received: from localhost.localdomain ([196.71.110.206]) by smtp.gmail.com with ESMTPSA id e2sm3531945wrd.60.2017.08.24.11.43.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Aug 2017 11:43:49 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: mw@semihalf.com, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Jingoo Han , Joao Pinto , Marc Zyngier , Rob Herring Subject: [PATCH v2 3/3] dt-bindings: designware: add binding for Designware PCIe in ECAM mode Date: Thu, 24 Aug 2017 19:43:21 +0100 Message-Id: <20170824184321.19432-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170824184321.19432-1-ard.biesheuvel@linaro.org> References: <20170824184321.19432-1-ard.biesheuvel@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Describe the binding for firmware-configured instances of the Synopsys Designware PCIe controller in RC mode. Cc: Rob Herring Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt new file mode 100644 index 000000000000..b8127b19c220 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt @@ -0,0 +1,56 @@ +* Synopsys Designware PCIe root complex in ECAM mode + +In some cases, firmware may already have configured the Synopsys Designware +PCIe controller in RC mode with static ATU window mappings that cover all +config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. +In this case, there is no need for the OS to perform any low level setup +of clocks or device registers, nor is there any reason for the driver to +reconfigure ATU windows for config and/or IO space accesses at runtime. + +Such hardware configurations should be described as "pci-host-ecam-generic" +if they are truly ECAM compatible. Configurations that require no low-level +setup by the OS nor any ATU window reconfiguration at runtime, but do +require special handling for type 0 config TLPs may instead be described as +"snps,dw-pcie-ecam". + +Required properties: +- compatible: should contain "snps,dw-pcie-ecam". + +Please refer to the binding document of "pci-host-ecam-generic" in the +file host-generic-pci.txt for a description of the remaining required +and optional properties. + + +* MSI support for Synopsys Designware PCIe root complex in ECAM mode + +Platforms that elect to perform all configuration of the RC in firmware +and use the "pci-host-ecam-generic" or "snps,dw-pcie-ecam" binding to +describe it to the OS may include a separate description of the embedded +MSI controller in case no MSI support is available in the core interrupt +controller. + +Required properties: +- compatible: should contain "snps,dw-pcie-msi". +- reg: a single region describing the device registers. +- interrupts: interrupt specifier for the interrupt that is asserted when + an MSI is received by the RC. +- msi-controller: empty property identifying this device as an MSI controller. + +Example for an implementation that routes all legacy INTx interrupts via SPI +#188 and all MSI interrupts via SPI #190: + + pcie@20000000 { + compatible = "snps,dw-pcie-ecam"; + device_type = "pci"; + msi-parent = <&msi0>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + ... + }; + + msi0: msi@10000000 { + compatible = "snps,dw-pcie-msi"; + reg = <0x0 0x10000000 0x0 0x10000>; + interrupts = ; + msi-controller; + };