From patchwork Mon Aug 28 10:53:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 9925299 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 37E5860311 for ; Mon, 28 Aug 2017 11:11:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C92C2869D for ; Mon, 28 Aug 2017 11:11:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2134B286BC; Mon, 28 Aug 2017 11:11:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EBE7B2869D for ; Mon, 28 Aug 2017 11:10:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751234AbdH1LKg (ORCPT ); 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dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD017.mail.protection.outlook.com (10.1.14.105) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1341.15 via Frontend Transport; Mon, 28 Aug 2017 11:10:33 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id v7SB9vXQ006251; Mon, 28 Aug 2017 04:10:29 -0700 From: Zhiqiang Hou To: , , , CC: , , , , , Hou Zhiqiang Subject: [PATCHv5 9/9] PCI: dwc: remove the obsolete fixups Date: Mon, 28 Aug 2017 18:53:01 +0800 Message-ID: <20170828105301.8511-10-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170828105301.8511-1-Zhiqiang.Hou@nxp.com> References: <20170828105301.8511-1-Zhiqiang.Hou@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131483922334266959; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2264 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Hou Zhiqiang Now, the dw_pcie_setup_rc() works well, so remove the obsolete fixups: Remove the Class field fix code from layerscape pcie driver. Remove the line to enable write permission of DBI RO register from artpec6 pcie driver. Signed-off-by: Hou Zhiqiang Acked-by: Roy Zang --- V5: - No change drivers/pci/dwc/pci-layerscape.c | 9 --------- drivers/pci/dwc/pcie-artpec6.c | 6 ------ 2 files changed, 15 deletions(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 65f5d543fe89..c24dd77c6424 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -73,14 +73,6 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); } -/* Fix class value */ -static void ls_pcie_fix_class(struct ls_pcie *pcie) -{ - struct dw_pcie *pci = pcie->pci; - - iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE); -} - /* Drop MSG TLP except for Vendor MSG */ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) { @@ -145,7 +137,6 @@ static int ls_pcie_host_init(struct pcie_port *pp) ls_pcie_disable_outbound_atus(pcie); dw_pcie_dbi_ro_wr_en(pci); - ls_pcie_fix_class(pcie); ls_pcie_clear_multifunction(pcie); dw_pcie_dbi_ro_wr_dis(pci); diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index 5d81f1d884e3..d153491f600f 100644 --- a/drivers/pci/dwc/pcie-artpec6.c +++ b/drivers/pci/dwc/pcie-artpec6.c @@ -141,12 +141,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); usleep_range(100, 200); - /* - * Enable writing to config regs. This is required as the Synopsys - * driver changes the class code. That register needs DBI write enable. - */ - dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); - /* setup root complex */ dw_pcie_setup_rc(pp);