From patchwork Mon Aug 28 18:04:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9925955 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1417660329 for ; Mon, 28 Aug 2017 18:04:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0502E2876C for ; Mon, 28 Aug 2017 18:04:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EDE4528780; Mon, 28 Aug 2017 18:04:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 86B432876C for ; Mon, 28 Aug 2017 18:04:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751271AbdH1SEw (ORCPT ); Mon, 28 Aug 2017 14:04:52 -0400 Received: from mail-wr0-f172.google.com ([209.85.128.172]:35657 "EHLO mail-wr0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751232AbdH1SEv (ORCPT ); Mon, 28 Aug 2017 14:04:51 -0400 Received: by mail-wr0-f172.google.com with SMTP id j29so2903299wre.2 for ; Mon, 28 Aug 2017 11:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JicZgUtJKFKCyCXsainIVAsegpoGPs4jV0M0QQ1q6CU=; b=hBy4o9Meg9ovo9OqqGd1b4GnqjxS5bpOKl4yFvrobMda5X9dlKgzl5LbOcWXcfeXjE SWfj2G5M3Y8W/sLpWA5Z3Pp2jonkvvjWD15eUObXahtF+UziefEB0GsyZtAF7XmRez8J izCDys33Ln0SfZ1L+HGjrBgfuZ9tQfkn0uPp4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JicZgUtJKFKCyCXsainIVAsegpoGPs4jV0M0QQ1q6CU=; b=PJiIoHAGVHZd4BL8bAD/VPY/juR+Umrk1m4Jbf6CxE11Dz+b/n7dOpRJAbm60rRn4f KPdOhEfwTCVz8PZk9ian1r31SV/ogDga2ZWTQKN0cWxkFhHSJkg1fAHXahPCpEj88Vi3 snKAruUDFSj+UkC/Mbp70659fOFaguu3nZ+POVr17TfKwjn2B9esg1octT4T1j+OUj7u ovohT8SFpEEPC+xgJWcD1wA+xyDVOXw5L9cqItC7A1SAvcuiAXOmeK9YCYomupSeNEZJ +7bLfWltKF9MC8lY/xdQG4LFUVXasIl5E/hNYMd8tsPV3iHCiXsq7y1add0kMTRwtxiW i07w== X-Gm-Message-State: AHYfb5gXXzJ56QSQvvANcA/KbOC7T8vlVWk9mgGHcUUKGKniKh04OKsP Aa2TM6Jekx9rXbYD69/c9g== X-Received: by 10.223.174.165 with SMTP id y34mr1048264wrc.184.1503943490307; Mon, 28 Aug 2017 11:04:50 -0700 (PDT) Received: from localhost.localdomain ([105.133.189.215]) by smtp.gmail.com with ESMTPSA id i22sm1335922wrf.18.2017.08.28.11.04.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 11:04:49 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, mw@semihalf.com, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Jingoo Han , Joao Pinto , Rob Herring Subject: [PATCH v3 2/2] dt-bindings: designware: add binding for Designware PCIe in ECAM mode Date: Mon, 28 Aug 2017 19:04:37 +0100 Message-Id: <20170828180437.2646-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170828180437.2646-1-ard.biesheuvel@linaro.org> References: <20170828180437.2646-1-ard.biesheuvel@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Describe the binding for firmware-configured instances of the Synopsys Designware PCIe controller in RC mode, that are almost but not quite ECAM compliant. Cc: Rob Herring Signed-off-by: Ard Biesheuvel Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 42 ++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt new file mode 100644 index 000000000000..29bad1337c87 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt @@ -0,0 +1,42 @@ +* Synopsys Designware PCIe root complex in ECAM mode + +In some cases, firmware may already have configured the Synopsys Designware +PCIe controller in RC mode with static ATU window mappings that cover all +config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. +In this case, there is no need for the OS to perform any low level setup +of clocks, PHYs or device registers, nor is there any reason for the driver +to reconfigure ATU windows for config and/or IO space accesses at runtime. + +In cases where the IP was synthesized with a minimum ATU window size of +64 KB, it cannot be supported by the generic ECAM driver, because it +requires special config space accessors that filter accesses to device #1 +and beyond on the first bus. + +Required properties: +- compatible: "marvell,armada8k-pcie-ecam" or + "socionext,synquacer-pcie-ecam" or + "snps,dw-pcie-ecam" (must be preceded by a more specific match) + +Please refer to the binding document of "pci-host-ecam-generic" in the +file host-generic-pci.txt for a description of the remaining required +and optional properties. + +Example: + + pcie1: pcie@7f000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x7f000000 0x0 0xf00000>; + bus-range = <0x0 0xe>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, + <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; + msi-map = <0x0 &its 0x0 0x10000>; + dma-coherent; + };