From patchwork Mon Oct 2 04:17:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 9980215 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 776B9602A0 for ; Mon, 2 Oct 2017 04:17:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66B7C1FFAD for ; Mon, 2 Oct 2017 04:17:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5BB2428173; Mon, 2 Oct 2017 04:17:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B04DB1FFAD for ; Mon, 2 Oct 2017 04:17:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751318AbdJBERE (ORCPT ); Mon, 2 Oct 2017 00:17:04 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:32817 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751255AbdJBERD (ORCPT ); Mon, 2 Oct 2017 00:17:03 -0400 Received: by mail-pf0-f193.google.com with SMTP id m28so4286497pfi.0 for ; Sun, 01 Oct 2017 21:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=45/E3QuaAZPT3zFwziwbAY3MaPLljTyNMuwO6cV1YjA=; b=uHjVOwDW7fM6jMDrE9Ph9YshqT74clETlr4l3j8kg6JkmaqirNg8dt5Tlsk1AsxNZC qBIguCd4LOTHpsxXwn01VKt6foGmEpODL9kPpDssEVkFtNAmYFUHSQBMBH9CRn5c2qC1 tWRj6aVPlI8iCBY40zoa+w0LUMXwQFrC3qftYMo36xjvgZgaUePxXYbc2CAxQSRR0ze/ uQhLoUOsvAz+/gdkZT0yD8/qWMqhWBZpFNujllZHMoTA9ELWlqb9gw5UbbSMeyOOC3mc aMFn0cOSutNI9w15XTt+OqRtH7IbHY6uVN1dHzarZxe88l4u20zz8atNJonp8DFcSuh1 QC4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :references:mime-version:content-disposition:in-reply-to:user-agent; bh=45/E3QuaAZPT3zFwziwbAY3MaPLljTyNMuwO6cV1YjA=; b=EWxnrm2Xt/3MdN7l8EpaMS7Gjp+MN+UO7kgBuWcV5xGIuA6dIs15ch3efNTom6gvMD FHHDt3s89xaMAKjCnIQQ8BYbr9T6FdNGcTyOEstOe8GcZVp/vUOS3F+0qxfAIlOLitbd m0hRj7knLes78wuivVGs3lzjQ7ML6Lf32+RIPrstuO0i+OIhYCGMQCCrQgzvSoYmLV+S CvuUoHl2GLlqCVp7vvSMw7i6JwbfKUT5bu4GHP0HgmUYMRVEIxrSO3EqtsnHGii8sVZ+ nj/z9xOTUmyRVLR7fbL4JlhEJIo9Oj8+jddC4sK//BP1zBfa7NcNwj/6XFPLfIjSoJH8 nDuA== X-Gm-Message-State: AMCzsaWVY9eByACVIwfp0qyP8lLjTcX9hW/I6vG1ZnsSr2WPV9URA1xT sdUfOV3fk70aCijTDZ36eOc613rS X-Google-Smtp-Source: AOwi7QAyAKaUwklD9dtyA+9S4FNLkdQS2Pdf7t8obSj/KlK7rEnG++KuiOHG/1z4pN6VU8XwFkH4PQ== X-Received: by 10.98.73.67 with SMTP id w64mr123512pfa.338.1506917823274; Sun, 01 Oct 2017 21:17:03 -0700 (PDT) Received: from localhost.localdomain (c-69-181-250-163.hsd1.ca.comcast.net. [69.181.250.163]) by smtp.gmail.com with ESMTPSA id z1sm14642432pge.45.2017.10.01.21.17.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 01 Oct 2017 21:17:02 -0700 (PDT) Date: Sun, 1 Oct 2017 21:17:01 -0700 From: Yinghai Lu To: Zhou Wang Cc: Bjorn Helgaas , linux-pci@vger.kernel.org Subject: Re: [RFC PATCH] PCI: Fix prefetchable range broken in pci_bridge_check_ranges Message-ID: <20171002041700.GA3834@localhost.localdomain> References: <1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com> User-Agent: Mutt/1.9.0 (2017-09-02) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Sat, Sep 23, 2017 at 03:24:42PM +0800, Zhou Wang wrote: > -> pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0xffffffff) > > This will change the prefetch range of 00:00.0 in a time slot, so traffic of > 01:00.0 or 01:00.1 may be broken. > > In fact, we can get if one bridge supports 64bit range by the bottom 4bits of > prefetchable memory base/limit. Honestly speaking, I don't know why 1f82de10d6b1 > ("PCI/86: don't assume prefetchable ranges are 64bit") has added the double > check code. some chip even that flags say that 64bit is support from that bits, but its upper 32 bits actually can not be changed. > > So Can we remove the double checking of prefetchable range to avoid this problem? > > Signed-off-by: Zhou Wang > --- > drivers/pci/setup-bus.c | 14 -------------- > 1 file changed, 14 deletions(-) > > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c > index 958da7d..23010a9 100644 > --- a/drivers/pci/setup-bus.c > +++ b/drivers/pci/setup-bus.c > @@ -778,20 +778,6 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) > b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; > } > } > - > - /* double check if bridge does support 64 bit pref */ > - if (b_res[2].flags & IORESOURCE_MEM_64) { > - u32 mem_base_hi, tmp; > - pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, > - &mem_base_hi); > - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, > - 0xffffffff); > - pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); > - if (!tmp) > - b_res[2].flags &= ~IORESOURCE_MEM_64; > - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, > - mem_base_hi); > - } > } > > /* Helper function for sizing routines: find first available Maybe we can try this: only touch upper 32bits after we touched low 32bits ? diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 958da7db9033..2ac4d20e5c11 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -744,6 +744,7 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) u32 pmem; struct pci_dev *bridge = bus->self; struct resource *b_res; + int pref_memory_base_touched = 0; b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; b_res[1].flags |= IORESOURCE_MEM; @@ -769,6 +770,7 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) 0xffe0fff0); pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); + pref_memory_base_touched = 1; } if (pmem) { b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; @@ -780,7 +782,7 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) } /* double check if bridge does support 64 bit pref */ - if (b_res[2].flags & IORESOURCE_MEM_64) { + if (pref_memory_base_touched && b_res[2].flags & IORESOURCE_MEM_64) { u32 mem_base_hi, tmp; pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &mem_base_hi);