From patchwork Mon Oct 2 14:08:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9980861 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C44C3602A0 for ; Mon, 2 Oct 2017 14:08:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6F5528741 for ; Mon, 2 Oct 2017 14:08:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AB5F22890C; Mon, 2 Oct 2017 14:08:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A24E028741 for ; Mon, 2 Oct 2017 14:08:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751127AbdJBOIt (ORCPT ); Mon, 2 Oct 2017 10:08:49 -0400 Received: from mail-wm0-f49.google.com ([74.125.82.49]:43988 "EHLO mail-wm0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751106AbdJBOIt (ORCPT ); Mon, 2 Oct 2017 10:08:49 -0400 Received: by mail-wm0-f49.google.com with SMTP id m72so7657856wmc.0 for ; Mon, 02 Oct 2017 07:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=bsJIjRcjA8brbHqCLN09qznTNk3JVIUSZWQqLDH5y14=; b=C3lbf/nnwq5l71MSdQu8OLs/x2wbWXh5PfDC/EoauAnCuclzQTRKg1dRm60kZkMg5h x30U4N+ax9iq/qJuS33hEVUlvLlVljxdXyH0WcHi+De4Sja+AziTTC3LI1X9G8luI7FI 94dfZDBWEL5gLpnbGNenkwsBpxPrerzqMGIBc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bsJIjRcjA8brbHqCLN09qznTNk3JVIUSZWQqLDH5y14=; b=U1t7pgzGqXiDFF/aaA8QctlVtMNMl8RSRX5HENGBYyatvBhGnw50jIMS04iRrVVoKB ZcY46i/abSCHTe1Dj8Gh60wv8XZhfZMeqzl3i3ELAQ7aAYJddzNDp7rsS837dK5o9aHc n5iPWGpRM3iAXePnz2gyeguIsFKmL9Mmzve8VgHLxBLpw2rNaGqxI0wPWdeO72X/vvpf cXvAwH6aeOSSnIx6plvnRbf4L4DsdIiLr4+4JN6KMR7o5XL2r8O1jSMIMmi78bCHVXDr vU7HmXCJ80UdiBj5vtpzw/DVNfPl9+ZAGSXuJxIwOQAMnakO/eSM44paY3g5NP2s4Lh1 d3Bw== X-Gm-Message-State: AHPjjUgoyF0Eva6QK2YGfSJ64v5nfXnR9OzC2UE4SbKzONm3qlu/V5om oRpbJ7qad5z/beXbXiT4bLxM1UEA8Uc= X-Google-Smtp-Source: AOwi7QCBiuI9eARvs0Lvrw9ZKMI/47IhTGaOdWH/7Mn4wHx1+ruHQXcAaPZpyva3P5jVq1MG6y7wnw== X-Received: by 10.28.22.82 with SMTP id 79mr11971403wmw.70.1506953327661; Mon, 02 Oct 2017 07:08:47 -0700 (PDT) Received: from localhost.localdomain ([160.90.203.54]) by smtp.gmail.com with ESMTPSA id f11sm890498wra.79.2017.10.02.07.08.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 02 Oct 2017 07:08:46 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org, bhelgaas@google.com Cc: graeme.gregory@linaro.org, leif.lindholm@linaro.org, daniel.thompson@Linaro.org, Ard Biesheuvel Subject: [PATCH] PCI: aspm: deal with missing root ports in link state handling Date: Mon, 2 Oct 2017 15:08:40 +0100 Message-Id: <20171002140840.7767-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Even though it is unconventional, some PCIe host implementations omit the root ports entirely, and simply consist of a host bridge (which is not modeled as a device in the PCI hierarchy) and a link. When the downstream device is an endpoint, our current code does not seem to mind this unusual configuration. However, when PCIe switches are involved, the ASPM code assumes that any downstream switch port has a parent, and blindly derefences the bus->parent->self field of the pci_dev struct to chain the downstream link state to the link state of the root port. Given that the root port is missing, the link is not modeled at all, and nor is the link state, and attempting to access it results in a NULL pointer dereference and a crash. So let's avoid this by allowing the link state chain to terminate at the downstream port if no root port exists. Signed-off-by: Ard Biesheuvel --- drivers/pci/pcie/aspm.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 1dfa10cc566b..0bea8498b5a5 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -802,10 +802,14 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) /* * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe - * hierarchies. + * hierarchies. Note that some PCIe host implementations omit + * the root ports entirely, in which case a downstream port on + * a switch may become the root of the link state chain for all + * its subordinate endpoints. */ if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT || - pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE) { + pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE || + !pdev->bus->parent->self) { link->root = link; } else { struct pcie_link_state *parent;