From patchwork Thu Oct 12 20:52:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 10002885 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B3FF16028A for ; Thu, 12 Oct 2017 20:53:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A754928EC3 for ; Thu, 12 Oct 2017 20:53:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C54128EC5; Thu, 12 Oct 2017 20:53:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_HI,RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C1EA28EC3 for ; Thu, 12 Oct 2017 20:53:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752631AbdJLUxg (ORCPT ); Thu, 12 Oct 2017 16:53:36 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:53386 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755216AbdJLUwe (ORCPT ); Thu, 12 Oct 2017 16:52:34 -0400 Received: by mail-pf0-f182.google.com with SMTP id t188so4084730pfd.10 for ; Thu, 12 Oct 2017 13:52:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M59a2MWUFc59pio5vgxZFwzuTptuRuWlWliyAP1IwnI=; b=FSqgTwRIQbX26wtoYA3gAZrpTkeAmQQDyML6+pkBj2/jsKCHH9WW751v3FzSqo2vQU /6nwufavfDPHFXOh1+y0x4gyDJvWe0yyDA8kvOsS/MTicb8IJCyTmnl2fhN9s+CRgQue DOck96D+9mkGPf3LFcCn9x4Sbh3wk9dCODTJs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M59a2MWUFc59pio5vgxZFwzuTptuRuWlWliyAP1IwnI=; b=szwnzOKTpmm7RjrnwZP/9uFOqhwOfbFjV4SCb1FwtuxTIKr31+j/MTE//DY6TSMDeD MB3jSBPhyFvZzs3h3n4qw/7NZg8UPxaOrRTywBhtugnG+QzFkFBNzaA5semuEJkCuBPJ MH3UV4urZ4kzQrNOd5EH0iMpqFFoYOAV82Is23/G5a8VIr15mNfiVLC6/zr73ZE9ryHE BG2NA0FA8qQqFP0C2Gzozqlt+r2yXS7AsY4IVsSSNfs/zDn/IjVtvzzkXZ9YL+/rSTik dsoawD0hLVMPsxVirCrquWMXQKUL2A5u455pA0cNw7H9ar1yDPjGydKPpzuWw7/Qsqub uQ0w== X-Gm-Message-State: AMCzsaUT0yZdLbCmoFJ/sSu7WKgFXOZdDznl82Ctzm2gmkoMDDe6nRiT x9TU3G2PYVoPIzbGkGw7mPdWjw== X-Google-Smtp-Source: AOwi7QBFg6hT6PSZpbRbQ05GwZJwDE5L2JPAfN0IrHPSNjINUKUl4J3mkIZhKcyOJm4lelHxh55/LQ== X-Received: by 10.159.255.12 with SMTP id bi12mr1160728plb.61.1507841554349; Thu, 12 Oct 2017 13:52:34 -0700 (PDT) Received: from ban.mtv.corp.google.com ([172.22.113.17]) by smtp.gmail.com with ESMTPSA id h1sm25048704pgp.37.2017.10.12.13.52.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Oct 2017 13:52:33 -0700 (PDT) From: Brian Norris To: Bjorn Helgaas Cc: Rajat Jain , Rob Herring , Mark Rutland , Frank Rowand , Shawn Lin , Heiko Stuebner , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Brian Norris Subject: [PATCH 3/3] PCI: rockchip: Support configuring PERST# state via DT Date: Thu, 12 Oct 2017 13:52:20 -0700 Message-Id: <20171012205220.130048-4-briannorris@chromium.org> X-Mailer: git-send-email 2.15.0.rc0.271.g36b669edcc-goog In-Reply-To: <20171012205220.130048-1-briannorris@chromium.org> References: <20171012205220.130048-1-briannorris@chromium.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I've found that different endpoints and board configurations have required different behavior from the PCIe Reset (PERST#) signal when in low-power system suspend (e.g., S3). Use the new of_pci helper to request this state and assert (active low) PERST# before suspending. Note that we reinitialize the link (including reconfiguring PERST#) at resume time. This requires that the board and system firmware supports driving this signal low when the system is suspended, since PERST# may be pulled up by the endpoint, and some GPIO banks are not active in S3. Signed-off-by: Brian Norris --- drivers/pci/host/pcie-rockchip.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 9051c6c8fea4..1ab58c1abb34 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -233,6 +233,7 @@ struct rockchip_pcie { struct regulator *vpcie1v8; /* 1.8V power supply */ struct regulator *vpcie0v9; /* 0.9V power supply */ struct gpio_desc *ep_gpio; + bool suspend_reset; u32 lanes; u8 lanes_map; u8 root_bus_nr; @@ -1155,6 +1156,9 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) dev_info(dev, "no vpcie0v9 regulator found\n"); } + /* Default not-asserted, to retain backward compatibility. */ + rockchip->suspend_reset = of_pci_get_pcie_reset_suspend(node) > 0; + return 0; } @@ -1463,6 +1467,9 @@ static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) return ret; } + if (rockchip->suspend_reset) + gpiod_set_value(rockchip->ep_gpio, 0); + rockchip_pcie_deinit_phys(rockchip); rockchip_pcie_disable_clocks(rockchip);