From patchwork Fri Dec 1 06:13:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10086315 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CEC1C6035E for ; Fri, 1 Dec 2017 06:14:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC0E42A476 for ; Fri, 1 Dec 2017 06:14:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B0D022A509; Fri, 1 Dec 2017 06:14:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6576B2A476 for ; Fri, 1 Dec 2017 06:14:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752688AbdLAGN2 (ORCPT ); Fri, 1 Dec 2017 01:13:28 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:56460 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752647AbdLAGN0 (ORCPT ); Fri, 1 Dec 2017 01:13:26 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vB16D12G000595; Fri, 1 Dec 2017 00:13:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1512108781; bh=TSFnK7Cfzxp9JSkebwbdYIeGPTKlMVMSd0523nXsesM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HqbaQu2ysjVfkDkwKKNUfX9hsdJCm+zJCrsGMBK+mULYrww4A5bZ47719JDeFDXap ipyIqMxjxNh/Rf8zAhIPKzpvqxEotIerA8GcC+mjXDOThrRAUlMf3Habahk91Mkh4W ReYmZgepgSyCM8kpUT5FFeaG4j9HC3+OKzwC4YgQ= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16D03x021896; Fri, 1 Dec 2017 00:13:00 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 1 Dec 2017 00:13:00 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 1 Dec 2017 00:13:00 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16CjTd013757; Fri, 1 Dec 2017 00:12:57 -0600 From: Vignesh R To: Bjorn Helgaas , Rob Herring , Tony Lindgren , Chris Welch CC: Kishon Vijay Abraham I , Lorenzo Pieralisi , , , , , , Vignesh R Subject: [PATCH 3/4] ARM: dts: dra7: Add DT property to allow unaligned mem access to PCIe RC Date: Fri, 1 Dec 2017 11:43:10 +0530 Message-ID: <20171201061311.16691-4-vigneshr@ti.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171201061311.16691-1-vigneshr@ti.com> References: <20171201061311.16691-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add ti,syscon-unaligned-access property to PCIe RC nodes in order to enable workaround for errata i870 in PCIe RC mode as well. Signed-off-by: Vignesh R --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ac9216293b7c..e4182f4cc36d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -314,6 +314,7 @@ <0 0 0 2 &pcie1_intc 2>, <0 0 0 3 &pcie1_intc 3>, <0 0 0 4 &pcie1_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; status = "disabled"; pcie1_intc: interrupt-controller { interrupt-controller; @@ -367,6 +368,7 @@ <0 0 0 2 &pcie2_intc 2>, <0 0 0 3 &pcie2_intc 3>, <0 0 0 4 &pcie2_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; pcie2_intc: interrupt-controller { interrupt-controller; #address-cells = <0>;