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Wed, 29 Aug 2018 03:07:14 +0000 Date: Wed, 29 Aug 2018 11:04:08 +0800 From: Jisheng Zhang To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Lorenzo Pieralisi , , , Subject: [PATCH v3] PCI: dwc: fix scheduling while atomic issues Message-ID: <20180829110408.556c3622@xhacker.debian> X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-Originating-IP: [124.74.246.114] X-ClientProxiedBy: KAWPR01CA0090.jpnprd01.prod.outlook.com (2603:1096:402:c::26) To CY1PR0301MB1579.namprd03.prod.outlook.com (2a01:111:e400:529c::17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 80f58c90-e7a3-4fcd-fa2f-08d60d5c8658 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989137)(5600074)(711020)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060)(7193020);SRVR:CY1PR0301MB1579; X-Microsoft-Exchange-Diagnostics: 1;CY1PR0301MB1579;3:ZmdUgBFmUsuzpdlBPdCpYEppvtJSkyX7PtWClKTkvdKichTxavcaMFHnr0u2WVck7dJp6HymEEq7tvLg0BMcwqJ5etJgsQwAtAb77Rw+pPTrcKtZpC4rNt1TmP5Pubj2Aql6VmDd/T+4qSpWXUKUXOhrrU7NOWYfeq/Pb32eyNVRYU3LuX+dWErRUyNKVTplQ+kU9obQAA2lQ1OXDImD+77tpCUyZg+jBN7olMVAIzzy3dwvBusrkjxlkgPFZN5P;25:N05uj38x8SCu9qTWZ86Aory8Hl3a0+W4NAdM4Rb/0pwZl9Mu9fa4GJwDqN2eYOqEQoRX/LP5n8wT6vVK3bYU9+gmHs6CGC89LpDhb0LwK2GYSUIHQHqrhX2YDRmyTGhiWKkF8C0JYDDUvmNjM4aAxS6P09xL4o71wC2D1lJYjkmDS9QMWFtsY0N9Hya0fTCRGb+snVK5SCwP/gwVMkI2PK5XcbaWKxBXE9ZHx5NrjzrBmqYEQ4VNIk553rP2KU9nSiVYswPEhbimtrnraOkTQOx80sYSz/oLIfJbltUHWmjwg1kk9j/5DX+neXWOXKPh3jdqwvS8oZzcwgoTZuLXqw==;31:s1ITjxvIPE4o+L1YVP9P9LvVZTNAa4eHpj3Qw7fWxvrhAtIoTMsJonlmOHM+A0qXRg8EtXyTat/aC08uQY78ICKPtkBoaxlbzcR8WM3pB0wzgu8pDtYMW32VIBFVUdR6Y0FWrW1/Fkz8nbgru6alvfNe0mjcYXOXu8RFUtChZ+QH/A8qBvSg8c4SdoYjBP5W8nYr+OkngeNtwGJmSEkI47qB9nftNtyEUp5i1LXXPa4= X-MS-TrafficTypeDiagnostic: CY1PR0301MB1579: X-Microsoft-Exchange-Diagnostics: 1;CY1PR0301MB1579;20:R0+iHMLI3A3NoN6hEZWuvDb/As2gjRvhr6WMedR55i88QCycFAjudDQchIn9Q44frGfFIMqDTQPFVLE0nNCbEcYoLCZK1i4znTdG6h84jbcmc4Kkf6OyfwaglxxMOueVHM38kK2uyJgOahwRATe1GwanSf9URZ2w+BJnaVe9b3d5Fe86WOaBcS/uEGUxR3aQFkwkheClaJldLpj9p7BXfFb6mOKsmsiL9sQZRbU1OoO70WmqFWFXZZMrQ3Yb0pP3Qb0sK9fpYCGPPQkEM6Lg31D/zAheu6eSEetq7Cr/epB3OYdgMFw/i2K5/8kkdyBbokX0tJCFhXWAW8vcwkOM2yH/hTJ1Ebx3uQRtl/aRSCwlvNJU5T0vyrLHHsnR7rwBUsegP5Ly8To2anP48v7xVaG2/0FF45BmA4/N5uCBXLZ/PicH8/1xd8K/HDBVfxQx3S4UBhwoUeaEyuoBs4DI7Mr5MMkKIKPYPMI5Yn1oYBxZUjhFjkyRDrnFWWYn33r1;4:8CgtAvGBJgoqMNmNoJIo5recIp8ihAQRq13woV2uQQmx0jvjfyP+iCu9XOkCvL7w2YcosEyGdV79VeFjJPHnFTFLYfzdOnFKvJzkKCgEgpYSR6y7KphceWsEOsDA0xV0C3QgZOI/P8/nSw4hUcvWcmaqEIfTfJ9QEfMyPUv2SOiTU+cXvl6sr8e7Uc7a+UAOzMeG1ULOwMYtiKuwy5bkCJgCEnaj/UN0H/VOrd4Syy1/saiadEZtpzTfO707KmZcRQC+ORPtpNFbaMfm2L4RwA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; 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Unfortunately, the atu programming can be called in atomic context: inbound atu programming could be called through pci_epc_write_header() =>dw_pcie_ep_write_header() =>dw_pcie_prog_inbound_atu() outbound atu programming could be called through pci_bus_read_config_dword() =>dw_pcie_rd_conf() =>dw_pcie_prog_outbound_atu() Fix this issue by calling mdelay() instead. Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Fixes: d8bbeb39fbf3 ("PCI: designware: Wait for iATU enable") Signed-off-by: Jisheng Zhang Acked-by: Gustavo Pimentel --- since v2: - Add Fixes tag - Add Gustavo's Ack since v1: - use mdelay() instead of udelay() to avoid __bad_udelay() drivers/pci/controller/dwc/pcie-designware.c | 8 ++++---- drivers/pci/controller/dwc/pcie-designware.h | 3 +-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 778c4f76a884..2153956a0b20 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -135,7 +135,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, if (val & PCIE_ATU_ENABLE) return; - usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); + mdelay(LINK_WAIT_IATU); } dev_err(pci->dev, "Outbound iATU is not being enabled\n"); } @@ -178,7 +178,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, if (val & PCIE_ATU_ENABLE) return; - usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); + mdelay(LINK_WAIT_IATU); } dev_err(pci->dev, "Outbound iATU is not being enabled\n"); } @@ -236,7 +236,7 @@ static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, if (val & PCIE_ATU_ENABLE) return 0; - usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); + mdelay(LINK_WAIT_IATU); } dev_err(pci->dev, "Inbound iATU is not being enabled\n"); @@ -282,7 +282,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar, if (val & PCIE_ATU_ENABLE) return 0; - usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); + mdelay(LINK_WAIT_IATU); } dev_err(pci->dev, "Inbound iATU is not being enabled\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 96126fd8403c..9f1a5e399b70 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -26,8 +26,7 @@ /* Parameters for the waiting for iATU enabled routine */ #define LINK_WAIT_MAX_IATU_RETRIES 5 -#define LINK_WAIT_IATU_MIN 9000 -#define LINK_WAIT_IATU_MAX 10000 +#define LINK_WAIT_IATU 9 /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710