| Message ID | 20181120092615.11680-11-Zhiqiang.Hou@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs | expand |
reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> > -----Original Message----- > From: Z.q. Hou > Sent: Tuesday, November 20, 2018 5:27 PM > To: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li > <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com; > catalin.marinas@arm.com; will.deacon@arm.com > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q. Hou > <zhiqiang.hou@nxp.com> > Subject: [PATCHv2 10/25] PCI: mobiveil: fix the INTx process error > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > In the loop block, there is not code change the loop key, this patch updated > the loop key by re-read the INTx status register. > > This patch also change to clear the handled INTx status. > > Note: Need MV to test this fix. > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > V2: > - Added fixes entry. > > drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > b/drivers/pci/controller/pcie-mobiveil.c > index 4ba458474e42..78e575e71f4d 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) > /* Handle INTx */ > if (intr_status & PAB_INTP_INTX_MASK) { > shifted_status = csr_readl(pcie, > PAB_INTP_AMBA_MISC_STAT); > + shifted_status &= PAB_INTP_INTX_MASK; > shifted_status >>= PAB_INTX_START; > do { > for_each_set_bit(bit, &shifted_status, > PCI_NUM_INTX) { @@ -372,12 +373,16 @@ static void > mobiveil_pcie_isr(struct irq_desc *desc) > dev_err_ratelimited(dev, > "unexpected IRQ, INT%d\n", > bit); > > - /* clear interrupt */ > - csr_writel(pcie, > - shifted_status << PAB_INTX_START, > + /* clear interrupt handled */ > + csr_writel(pcie, 1 << (PAB_INTX_START + bit), > PAB_INTP_AMBA_MISC_STAT); > } > - } while ((shifted_status >> PAB_INTX_START) != 0); > + > + shifted_status = csr_readl(pcie, > + > PAB_INTP_AMBA_MISC_STAT); > + shifted_status &= PAB_INTP_INTX_MASK; > + shifted_status >>= PAB_INTX_START; > + } while (shifted_status != 0); > } > > /* read extra MSI status register */ > -- > 2.17.1
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 4ba458474e42..78e575e71f4d 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) /* Handle INTx */ if (intr_status & PAB_INTP_INTX_MASK) { shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); + shifted_status &= PAB_INTP_INTX_MASK; shifted_status >>= PAB_INTX_START; do { for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit); - /* clear interrupt */ - csr_writel(pcie, - shifted_status << PAB_INTX_START, + /* clear interrupt handled */ + csr_writel(pcie, 1 << (PAB_INTX_START + bit), PAB_INTP_AMBA_MISC_STAT); } - } while ((shifted_status >> PAB_INTX_START) != 0); + + shifted_status = csr_readl(pcie, + PAB_INTP_AMBA_MISC_STAT); + shifted_status &= PAB_INTP_INTX_MASK; + shifted_status >>= PAB_INTX_START; + } while (shifted_status != 0); } /* read extra MSI status register */