From patchwork Tue Nov 20 09:27:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 10690089 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E9D6E14E2 for ; Tue, 20 Nov 2018 09:28:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D98A12A0D5 for ; Tue, 20 Nov 2018 09:28:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CCD4E2A197; Tue, 20 Nov 2018 09:28:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 706E12A0D5 for ; Tue, 20 Nov 2018 09:28:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727744AbeKTT4M (ORCPT ); Tue, 20 Nov 2018 14:56:12 -0500 Received: from mail-eopbgr70054.outbound.protection.outlook.com ([40.107.7.54]:9376 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727453AbeKTT4L (ORCPT ); Tue, 20 Nov 2018 14:56:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EsWc3HHrsvCw3TAwiGTFo3m6TFcG6WSs2Q/TCpBa6hQ=; b=O6Wz3zKZW874i7b2OoGIyiiPnTX/l6Br6wt4MiObbqcq/ESmFTTTmosnnYEfBq4D/CSetptjNLlMrWhoSx7zFqLQ1Cjm7vCxjpwN+tWP1DlRD7BGJmWRo4t2cWdx1xzcOmzVPQ0U12asP+M5cS9gHbgHLimRbKaodKFCr+RS69k= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:57 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:57 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 23/25] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Thread-Topic: [PATCHv2 23/25] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Thread-Index: AQHUgLNSP5Bm4CVLVUSREMlUOF4EKw== Date: Tue, 20 Nov 2018 09:27:57 +0000 Message-ID: <20181120092615.11680-24-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM6PR04MB4775;6:oLnUSrZeyDiIt0kSqpvfhdkF4T1mhgt/COeKl+5I+uCUZqXX4eZcQGG69OhZHReemH/7o+B0El0YjxL5EQhXeu4BXLSWAI7W+omDAZogf9Wfq+mwyD/Nb2LR0gr5pS+th89vOGcMcfPfLfUaBG+pzWA0R27ZdxhN5m4BOq/xYOreBX1UD1RHmhQg8T8MC03Yh7XMP+VCSQgPG8Fx6gmsdBfo+tKIKJBbT/nCP9f6tCSmYVjLCqGg1kTOLoC6h6lg3xxp4zGuP1l/U6wXr9m79DJVq/yEwFNIfT0/MRGSrc5dEAgShyUW9gd6MuIp0/us9/QoFQRgBnm8kXKlsufMzbKOoEo6mot4kbWEzbV+gZz8sgNduDnPh0G9/CK1c0BqusrjwphfhAfrEsMZJSt63EBkxdiBC2UtQiAXGHrNs8IK77TjNM3N8QFjJKjQAJuF037aFLhVuEtwgIrxF9i0xw==;5:htHl+EBHmc/sCJcdFY7Q9CyAzvE/VGvF2vaPyXl3BLVHJ4KPth8C8fRv56P00gL7nyugIoMg6jVuGHioBXzL+0HQ/wQo1gk2Pp1sVzfTF06Os5p8iU/GFDfXXXyFARbBdcasbIWa2YAZfFEdbnZhhdRe9AADo2UBz73frf6fvDY=;7:bvCuqQYJQ1mWOWGJ8LgKjWAXXAA//I3xEY26p+2fp9HQJbOxW7DsdQtl4kXsMCC9YWJQUmDzmjjA5MhnHfpafqCR7dhhBnLtvdrfvmkueBRU450Mi7lX9I2U9vUlv1VQxVFibHngvXh9ewnGI9E8Xw== x-ms-office365-filtering-correlation-id: 71340e26-cd9b-4209-1975-08d64eca751b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095);SRVR:AM6PR04MB4775;BCL:0;PCL:0;RULEID:;SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6029001)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:AM6PR04MB4775;H:AM6PR04MB5781.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: nQjTqqLGwHw6f09lvx2CppTGmXJEmNZLNWiE09Bv2F8G+z68jN49kVX5lEMIWzwyS8zOcHabef0l8kn0AFklSzfyymymdY8morc7ck/rm+jC6waIvTHCECE9Ov16bl9gmMra2gj8jbIchgU1fENayxaNsIRim51aWXHaayg0snf98Kci+TRBQSlS3o4DxgWm6dok2tnTIzl4GF0c1epTxhR1Qh/mQqFVjvw1e3nTiUYvEz6hHNVKYP1xpaG72MBJxf0tcxYNgjtHfctOygUAnAhFQ1aUNISyBESqXPapNMZQdiwUwuQSLCMsBaJZNj9mLtrvmA1c3YltZ9z6Bir7wE1vVn/IkmpkLKPfoGNVj+c= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: <56EDB6A0BB4E1E40BF3180250A6DE33B@eurprd04.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 71340e26-cd9b-4209-1975-08d64eca751b X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:57.7074 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Hou Zhiqiang This PCIe controller is based on the Mobiveil GPEX IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Changed the name of functions and data structures in this driver. - Moved the reset operations to bottle half of the ISR. - Added timeout check in polling the status of the PAB. - Moved the interrupt init operations to ls_pcie_g4_interrupt_init(). drivers/pci/controller/mobiveil/Kconfig | 10 + drivers/pci/controller/mobiveil/Makefile | 1 + .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++++++++++++++++++ .../pci/controller/mobiveil/pcie-mobiveil.h | 16 +- 4 files changed, 279 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig index 64343c07bfed..3ddb7d6163a9 100644 --- a/drivers/pci/controller/mobiveil/Kconfig +++ b/drivers/pci/controller/mobiveil/Kconfig @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT Soft IP. It has up to 8 outbound and inbound windows for address translation and it is a PCIe Gen4 IP. +config PCI_LAYERSCAPE_GEN4 + bool "Freescale Layerscpe PCIe Gen4 controller" + depends on PCI + depends on OF && (ARM64 || ARCH_LAYERSCAPE) + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_MOBIVEIL_HOST + help + Say Y here if you want PCIe Gen4 controller support on + Layerscape SoCs. The PCIe controller can work in RC or + EP mode according to RCW[HOST_AGT_PEX] setting. endmenu diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile index 9fb6d1c6504d..ff66774ccac4 100644 --- a/drivers/pci/controller/mobiveil/Makefile +++ b/drivers/pci/controller/mobiveil/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c new file mode 100644 index 000000000000..174cbcac4059 --- /dev/null +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for NXP Layerscape SoCs + * + * Copyright 2018 NXP + * + * Author: Zhiqiang Hou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-mobiveil.h" + +/* LUT and PF control registers */ +#define PCIE_LUT_OFF (0x80000) +#define PCIE_PF_OFF (0xc0000) +#define PCIE_PF_INT_STAT (0x18) +#define PF_INT_STAT_PABRST (31) + +#define PCIE_PF_DBG (0x7fc) +#define PF_DBG_LTSSM_MASK (0x3f) +#define PF_DBG_WE (31) +#define PF_DBG_PABR (27) + +#define LS_PCIE_G4_LTSSM_L0 0x2d /* L0 state */ + +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev) + +struct ls_pcie_g4 { + struct mobiveil_pcie *pci; + struct delayed_work dwork; + int irq; +}; + +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off); +} + +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off); +} + +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off); +} + +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off); +} + +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 header_type; + + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); + u32 state; + + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + state = state & PF_DBG_LTSSM_MASK; + + if (state == LS_PCIE_G4_LTSSM_L0) + return 1; + + return 0; +} + +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 val, act_stat; + int to = 100; + + /* Poll for pab_csb_reset to set and PAB activity to clear */ + do { + usleep_range(10, 15); + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT); + act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT); + } while (((val & 1 << PF_INT_STAT_PABRST) == 0 || act_stat) && to--); + if (to < 0) { + dev_err(&mv_pci->pdev->dev, "poll PABRST&PABACT timeout\n"); + return; + } + + /* clear PEX_RESET bit in PEX_PF0_DBG register */ + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val |= 1 << PF_DBG_WE; + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val |= 1 << PF_DBG_PABR; + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val &= ~(1 << PF_DBG_WE); + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + mobiveil_host_init(mv_pci, true); + + to = 100; + while (!ls_pcie_g4_link_up(mv_pci) && to--) + usleep_range(200, 250); + if (to < 0) + dev_err(&mv_pci->pdev->dev, "PCIe link trainning timeout\n"); +} + +static irqreturn_t ls_pcie_g4_handler(int irq, void *dev_id) +{ + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id; + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 val; + + val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT); + if (!val) + return IRQ_NONE; + + if (val & PAB_INTP_RESET) + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); + + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT); + + return IRQ_HANDLED; +} + +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci); + u32 val; + int ret; + + pcie->irq = platform_get_irq_byname(mv_pci->pdev, "intr"); + if (pcie->irq < 0) { + dev_err(&mv_pci->pdev->dev, "Can't get 'intr' irq.\n"); + return pcie->irq; + } + ret = devm_request_irq(&mv_pci->pdev->dev, pcie->irq, + ls_pcie_g4_handler, IRQF_SHARED, + mv_pci->pdev->name, pcie); + if (ret) { + dev_err(&mv_pci->pdev->dev, "Can't register PCIe IRQ.\n"); + return ret; + } + + /* Enable interrupts */ + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET | + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC; + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB); + + return 0; +} + +static void ls_pcie_g4_reset(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, + work); + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork); + struct mobiveil_pcie *mv_pci = pcie->pci; + u16 ctrl; + + ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL); + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; + csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); + ls_pcie_g4_reinit_hw(pcie); +} + +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = { + .interrupt_init = ls_pcie_g4_interrupt_init, +}; + +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = { + .link_up = ls_pcie_g4_link_up, +}; + +static int __init ls_pcie_g4_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mobiveil_pcie *mv_pci; + struct ls_pcie_g4 *pcie; + struct device_node *np = dev->of_node; + int ret; + + if (!of_parse_phandle(np, "msi-parent", 0)) { + dev_err(dev, "failed to find msi-parent\n"); + return -EINVAL; + } + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL); + if (!mv_pci) + return -ENOMEM; + + mv_pci->pdev = pdev; + mv_pci->ops = &ls_pcie_g4_pab_ops; + mv_pci->rp.ops = &ls_pcie_g4_rp_ops; + pcie->pci = mv_pci; + + platform_set_drvdata(pdev, pcie); + + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset); + + ret = mobiveil_pcie_host_probe(mv_pci); + if (ret) { + dev_err(dev, "fail to probe!\n"); + return ret; + } + + if (!ls_pcie_g4_is_bridge(pcie)) + return -ENODEV; + + return 0; +} + +static const struct of_device_id ls_pcie_g4_of_match[] = { + { .compatible = "fsl,lx2160a-pcie", }, + { }, +}; + +static struct platform_driver ls_pcie_g4_driver = { + .driver = { + .name = "layerscape-pcie-gen4", + .of_match_table = ls_pcie_g4_of_match, + .suppress_bind_attrs = true, + }, +}; + +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 0f5303962e88..0ccd6cee5f8f 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -41,6 +41,8 @@ #define PAGE_LO_MASK 0x3ff #define PAGE_SEL_OFFSET_SHIFT 10 +#define PAB_ACTIVITY_STAT 0x81c + #define PAB_AXI_PIO_CTRL 0x0840 #define APIO_EN_MASK 0xf @@ -49,8 +51,18 @@ #define PAB_INTP_AMBA_MISC_ENB 0x0b0c #define PAB_INTP_AMBA_MISC_STAT 0x0b1c -#define PAB_INTP_INTX_MASK 0x01e0 -#define PAB_INTP_MSI_MASK 0x8 +#define PAB_INTP_RESET (0x1 << 1) +#define PAB_INTP_MSI (0x1 << 3) +#define PAB_INTP_INTA (0x1 << 5) +#define PAB_INTP_INTB (0x1 << 6) +#define PAB_INTP_INTC (0x1 << 7) +#define PAB_INTP_INTD (0x1 << 8) +#define PAB_INTP_PCIE_UE (0x1 << 9) +#define PAB_INTP_IE_PMREDI (0x1 << 29) +#define PAB_INTP_IE_EC (0x1 << 30) +#define PAB_INTP_MSI_MASK PAB_INTP_MSI +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\ + PAB_INTP_INTC | PAB_INTP_INTD) #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) #define WIN_ENABLE_SHIFT 0