From patchwork Thu Apr 11 17:03:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10896499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF0011805 for ; Thu, 11 Apr 2019 17:06:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98236285C4 for ; Thu, 11 Apr 2019 17:06:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BF5F288FC; Thu, 11 Apr 2019 17:06:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3ACE9285C4 for ; Thu, 11 Apr 2019 17:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726862AbfDKRGE (ORCPT ); Thu, 11 Apr 2019 13:06:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15346 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726646AbfDKRGE (ORCPT ); Thu, 11 Apr 2019 13:06:04 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 11 Apr 2019 10:05:47 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 11 Apr 2019 10:06:03 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 11 Apr 2019 10:06:03 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:06:03 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 11 Apr 2019 17:05:59 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH 24/30] arm64: tegra: Add PEX DPD states as pinctrl properties Date: Thu, 11 Apr 2019 22:33:49 +0530 Message-ID: <20190411170355.6882-25-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411170355.6882-1-mmaddireddy@nvidia.com> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555002347; bh=MIcVx9aZ8MnVctiujiT6b2YOgRyjm/kjybyaWIMal4c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=K0mT2w4mioALT1uGQoK2xmK5XR2Wa02HEPAEhmSXW0eOqDTlbB5p+YN07U6/verFi k69bp3cYOPZk/lPJqtJPevUkN39PrTHJ+1pJA07RPN16RL19S+8o5iqEcSNH1IqFmd wbrqF9WrhEqW5B/Ml07T3KvnULnjsfsQH8WuY53oQvRL12ZwtGU6a4/2N0EvFD7CIS jJVY62dgDdT1IaJcQuh2UaY3yrc4lGFltEk10BFqwZB160pJ2fBzt/lj+ckTKemlPo WDOYXbbZC7EPZ6NAPsXWO9Qr86RS+sfh6DBQc+jbxE/7L88HijLvzGf3FhE13oJlwJ THvcNPdXW4kuA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PEX DPD states as pinctrl properties to set in PCIe driver. In Tegra210 BIAS pads are not in power down mode when clamps are applied. So to set the pads in DPD, pass the PEX DPD states as pinctrl properties to PCIe driver. Signed-off-by: Manikanta Maddireddy --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a550c0a4d572..876e32e6d577 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -48,6 +48,11 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + + pinctrl-names = "pex-dpd-disable", "pex-dpd-enable"; + pinctrl-0 = <&pex_dpd_disable>; + pinctrl-1 = <&pex_dpd_enable>; + status = "disabled"; pci@1,0 { @@ -848,6 +853,20 @@ pins = "sdmmc3"; power-source = ; }; + + pex_dpd_disable: pex_en { + pex-dpd-disable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-disable; + }; + }; + + pex_dpd_enable: pex_dis { + pex-dpd-enable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-enable; + }; + }; }; fuse@7000f800 {