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[PATCHv5,14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers

Message ID 20190412083635.33626-15-Zhiqiang.Hou@nxp.com (mailing list archive)
State Superseded, archived
Headers show
Series PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver | expand

Commit Message

Z.Q. Hou April 12, 2019, 8:36 a.m. UTC 
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The reset value of Primary, Secondary and Subordinate bus numbers is
zero, so set a workable value for these 3 bus numbers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index db7ecb021c63..9210165fe8c0 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -582,6 +582,12 @@  static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 	u32 value, pab_ctrl, type;
 	struct resource_entry *win;
 
+	/* setup bus numbers */
+	value = csr_readl(pcie, PCI_PRIMARY_BUS);
+	value &= 0xff000000;
+	value |= 0x00ff0100;
+	csr_writel(pcie, value, PCI_PRIMARY_BUS);
+
 	/*
 	 * program Bus Master Enable Bit in Command Register in PAB Config
 	 * Space