From patchwork Sun May 26 04:37:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 10961255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0382A912 for ; Sun, 26 May 2019 04:39:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E602128A9D for ; Sun, 26 May 2019 04:39:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D910A28AA4; Sun, 26 May 2019 04:39:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7DDEB28A9D for ; Sun, 26 May 2019 04:39:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727702AbfEZEjJ (ORCPT ); Sun, 26 May 2019 00:39:09 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2691 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725825AbfEZEjJ (ORCPT ); Sun, 26 May 2019 00:39:09 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sat, 25 May 2019 21:39:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 May 2019 21:39:08 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 May 2019 21:39:08 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 26 May 2019 04:39:07 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 26 May 2019 04:39:07 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 26 May 2019 04:39:07 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sat, 25 May 2019 21:39:07 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V8 08/15] dt-bindings: Add PCIe supports-clkreq property Date: Sun, 26 May 2019 10:07:44 +0530 Message-ID: <20190526043751.12729-9-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190526043751.12729-1-vidyas@nvidia.com> References: <20190526043751.12729-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1558845548; bh=yimjKT1EhK3mLwu1u02JxytPgu0tocqFAg/P2NRK328=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Bp/k4u79+FBBLu7IkCRhF6FRxgN8UP3NefbYvnQIW2CYtsU082QvY0+v5Wzta3nUG MAKfawZFz1T2NCwePjq+1bS5LnAsQUPTQwkvguc63sLltOXNV56t6/KGNvA+0Qhx/8 QElcM7hkmIANnpbGLhM+GPvI9qYGXDAiNiDovd7WDkM0KzfZSDXQIBoB8sDbtnFZw6 IwuCAWVIzohPVsJpHS89pz1qrv4VpT/N7hNps6lpDtwTz79wcBusF3qiXHai55TWt5 eHb2CzVl3yWO7Wq4Mi67AxQGIczvBiV94ujyIKK+cAKS8foM88Tg+GPexmRrt98vjE EVxeQJmPn/kcA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some host controllers need to know the existence of clkreq signal routing to downstream devices to be able to advertise low power features like ASPM L1 substates. Without clkreq signal routing being present, enabling ASPM L1 sub states might lead to downstream devices falling off the bus. Hence a new device tree property 'supports-clkreq' is added to make such host controllers aware of clkreq signal routing to downstream devices. Signed-off-by: Vidya Sagar Reviewed-by: Rob Herring Reviewed-by: Thierry Reding --- Changes since [v7]: * None Changes since [v6]: * None Changes since [v5]: * s/Documentation\/devicetree/dt-bindings/ in the subject Changes since [v4]: * None Changes since [v3]: * Rebased on top of linux-next top of the tree Changes since [v2]: * None Changes since [v1]: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 92c01db610df..d132f9efeb3e 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -24,6 +24,11 @@ driver implementation may support the following properties: unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. +- supports-clkreq: + If present this property specifies that CLKREQ signal routing exists from + root port to downstream device and host bridge drivers can do programming + which depends on CLKREQ signal existence. For example, programming root port + not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. PCI-PCI Bridge properties -------------------------