From patchwork Mon Jul 1 12:40:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11025799 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5AAE9138D for ; Mon, 1 Jul 2019 12:40:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C96428628 for ; Mon, 1 Jul 2019 12:40:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 40D2B286DA; Mon, 1 Jul 2019 12:40:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CAF0428628 for ; Mon, 1 Jul 2019 12:40:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729003AbfGAMkk (ORCPT ); Mon, 1 Jul 2019 08:40:40 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9112 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727564AbfGAMkk (ORCPT ); Mon, 1 Jul 2019 08:40:40 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 01 Jul 2019 05:40:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 01 Jul 2019 05:40:37 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 01 Jul 2019 05:40:37 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 1 Jul 2019 12:40:37 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 1 Jul 2019 12:40:37 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 1 Jul 2019 12:40:37 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 01 Jul 2019 05:40:36 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V12 03/12] PCI: dwc: Perform dbi regs write lock towards the end Date: Mon, 1 Jul 2019 18:10:01 +0530 Message-ID: <20190701124010.7484-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701124010.7484-1-vidyas@nvidia.com> References: <20190701124010.7484-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561984834; bh=ZPHZdQUeNnmFMzPoXfbUAGXppKNf3wrULi+u6tKgtJQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Zy67QgQ6na4QFHRi80uCibc/8fqBuA1VI7f9BWLBkgOvOSIm2Rg0Zt5045B9mqMTv DgFtr4Am59P6TWV3eTCsjbk4lgCKB1pj1a94OQkhzS95g2QZGjHYOr2q43D36Y69KU eGD14AP7XAyUiC9vsD+lRfk6N2oQY7vhV47MsWhdwbiLqo+fmnRE2UiTuZaDoacoEQ JIlQ7TEqC6xIaeTvaVO3aH4esEBBvr4Mg808xzp1OGtZfNOtS2F2ZN3F3f8fP0akGA LFXUfBqNJ+aZym2YJ8jOxuL9QdqSzg7OhK/QL7Pp8AirgyngbeA5pP76u7BDdiCHkI xgfZ2eL0Da+7A== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of DesignWare core's DBI registers (a.k.a configuration space registers) are write-protected with a lock without enabling which they are read-only by default. These write-protected registers are implementation specific. Tegra194's BAR-0 register which is at offset 0x10 in the configuration space is an example. Current implementation in dw_pcie_setup_rc() API attempts to unlock those write-protected registers whenever they are updated and lock them back again for writing. This patch attempts to unlock all such write-protected registers for writing in the beginning of the API once and lock them back again towards the end to avoid bloating the API with multiple unlock/lock sequences for all those write-protected registers. Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Acked-by: Jingoo Han --- Changes since [v11]: * Modified commit message to make it explicit that write-protected registers are implementation specific. Changes since [v10]: * None Changes since [v9]: * None Changes since [v8]: * None Changes since [v7]: * None Changes since [v6]: * None Changes since [v5]: * Moved write enable to the beginning of the API and write disable to the end Changes since [v4]: * None Changes since [v3]: * None Changes since [v2]: * None Changes since [v1]: * None drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f93252d0da5b..d3156446ff27 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 val, ctrl, num_ctrls; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + /* + * Enable DBI read-only registers for writing/updating configuration. + * Write permission gets disabled towards the end of this function. + */ + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_setup(pci); if (!pp->ops->msi_host_init) { @@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); /* Setup interrupt pins */ - dw_pcie_dbi_ro_wr_en(pci); val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); val &= 0xffff00ff; val |= 0x00000100; dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); - dw_pcie_dbi_ro_wr_dis(pci); /* Setup bus numbers */ val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); @@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* Enable write permission for the DBI read-only register */ - dw_pcie_dbi_ro_wr_en(pci); /* Program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); - /* Better disable write permission right after the update */ - dw_pcie_dbi_ro_wr_dis(pci); dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); + + dw_pcie_dbi_ro_wr_dis(pci); } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);