From patchwork Wed Jul 24 17:48:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11057451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 83B3414DB for ; Wed, 24 Jul 2019 17:49:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CEAB287E0 for ; Wed, 24 Jul 2019 17:49:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 61316287E3; Wed, 24 Jul 2019 17:49:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 06DC3287E0 for ; Wed, 24 Jul 2019 17:49:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726897AbfGXRtW (ORCPT ); Wed, 24 Jul 2019 13:49:22 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9297 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725851AbfGXRtW (ORCPT ); Wed, 24 Jul 2019 13:49:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 24 Jul 2019 10:49:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 24 Jul 2019 10:49:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 24 Jul 2019 10:49:21 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 24 Jul 2019 17:49:21 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 24 Jul 2019 17:49:21 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 24 Jul 2019 17:49:21 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 24 Jul 2019 10:49:20 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V14 07/13] dt-bindings: PCI: designware: Add binding for CDM register check Date: Wed, 24 Jul 2019 23:18:18 +0530 Message-ID: <20190724174824.20933-8-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190724174824.20933-1-vidyas@nvidia.com> References: <20190724174824.20933-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563990559; bh=E/aw4YxpYMzZoF/fb0sIhaBoOx7TXMMRiEqsGgwyQns=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=X32N1TRiApYn7/B6yV9Q/LRN8hD438VUVS3c7tLShvir1OlDGiizCzs6U5JYwEhwm LxdWodbQklg9+wXQXGgpWbLKofS5/JQ19W3RYu3wnLZdRlk0RL1Nf0NN3eG+zj61tC EX2UrG6hsjJo1AV+HKeakagwF+oARXeyol8zupYexZ6sGlNHKHnj+nPAKNarFHVHY4 NdqfhxHfkP2FLV9eUlQ5jxNPmhties/EaskwfMRr1OQkF4xP1ZJ7xBEGjRXH5wKTdW wVWjJ40G6lzRYSlsvsjZ+tFbwI2Cyz9k5TyELN1Uv33UpZcWipajSkAp40W4br3qy+ CRK6MdcWfljeg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to enable CDM (Configuration Dependent Module) registers check for any data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers and iATU and DMA registers. Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook Version 4.90a. Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Reviewed-by: Rob Herring --- V14: * Added a full stop(.) at the end of commit message. V13: * None V12: * None V11: * None V10: * None V9: * None V8: * None V7: * Changed "enable-cdm-check" to "snps,enable-cdm-check" V6: * None V5: * None V4: * None V3: * Changed flag name from 'cdm-check' to 'enable-cdm-check' * Added info about Port Logic and DMA registers being part of CDM V2: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c060d0..3fba04da6a59 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -34,6 +34,11 @@ Optional properties: - clock-names: Must include the following entries: - "pcie" - "pcie_bus" +- snps,enable-cdm-check: This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2.