From patchwork Tue Aug 13 11:36:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11091909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC5DB14F7 for ; Tue, 13 Aug 2019 11:37:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC1F7285C9 for ; Tue, 13 Aug 2019 11:37:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C05D0285EB; Tue, 13 Aug 2019 11:37:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62E83285C9 for ; Tue, 13 Aug 2019 11:37:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727837AbfHMLh2 (ORCPT ); Tue, 13 Aug 2019 07:37:28 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:13640 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726890AbfHMLh2 (ORCPT ); Tue, 13 Aug 2019 07:37:28 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 13 Aug 2019 04:37:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 13 Aug 2019 04:37:27 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 13 Aug 2019 04:37:27 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 13 Aug 2019 11:37:27 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 13 Aug 2019 11:37:27 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 13 Aug 2019 04:37:27 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V16 07/13] dt-bindings: PCI: designware: Add binding for CDM register check Date: Tue, 13 Aug 2019 17:06:21 +0530 Message-ID: <20190813113627.27251-8-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190813113627.27251-1-vidyas@nvidia.com> References: <20190813113627.27251-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1565696259; bh=pDTT3nz5bfhOIhp9cJtrj5hKDO6VHq56vcI6FoFsZjA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=lv4ZThaxb7syeLtSRD5NzXezUZiDTYCtmXOhlxDH6JEzzvVIs3x6UsRvxVFPeRRLG dAxlqrNghgchBsoXrmJAs3zjA61ah61sWtrS2FqVxenDEHBooWVFaJ+9Nshir+JiVH Df26d93zxRSt/+qODY/lYVW/D7oLY6wKr/OdjOVpZi17CU2/9GG3Av3Qw4G7tR1Hx7 8KoiDoYscfF1dgN6VdMxQa8rMejQh/FZJbKPnqX0wMfTNSPgRXfgBqtJxfFmIRIxD0 Dlw/Q4T2LTvuL/TS27iYCN2QyOZM1DEsaImTv2uK1gc/ldb3DJNP/p5kPTG10oljwq K3puQ2Q7h+row== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to enable CDM (Configuration Dependent Module) registers check for any data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers and iATU and DMA registers. Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook Version 4.90a. Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Reviewed-by: Rob Herring --- V16: * None V15: * None V14: * Added a full stop(.) at the end of commit message. V13: * None V12: * None V11: * None V10: * None V9: * None V8: * None V7: * Changed "enable-cdm-check" to "snps,enable-cdm-check" V6: * None V5: * None V4: * None V3: * Changed flag name from 'cdm-check' to 'enable-cdm-check' * Added info about Port Logic and DMA registers being part of CDM V2: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c060d0..3fba04da6a59 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -34,6 +34,11 @@ Optional properties: - clock-names: Must include the following entries: - "pcie" - "pcie_bus" +- snps,enable-cdm-check: This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2.