From patchwork Mon Dec 9 09:21:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11278681 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7468814B7 for ; Mon, 9 Dec 2019 09:21:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 51AF62077B for ; Mon, 9 Dec 2019 09:21:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="GVZ2NItQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727598AbfLIJVL (ORCPT ); Mon, 9 Dec 2019 04:21:11 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59902 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727619AbfLIJVK (ORCPT ); Mon, 9 Dec 2019 04:21:10 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99L3NC046038; Mon, 9 Dec 2019 03:21:03 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883263; bh=f4oXcQEVxFFKqAFQ41+Ixwr9LBwG0bHt8f5qwBY+dkI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GVZ2NItQK/iNov5YRB2xmesxldtYQDIUEG0D09p3eDs/8gqwkHUBxrZFzkSog+oth wwcXafHTl1wpJjLE8g/bCMS0O8ob/UJpBkQULG4voHAKTClZdHlN2Bvp8RMmIoI674 6SGPukoDkujgh4rTS2ZyvMq9i9WWhBNorP22Ch18= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99L2au127280; Mon, 9 Dec 2019 03:21:03 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:02 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:02 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd4087697; Mon, 9 Dec 2019 03:20:59 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Date: Mon, 9 Dec 2019 14:51:40 +0530 Message-ID: <20191209092147.22901-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 7 ++++--- drivers/pci/controller/cadence/pcie-cadence.h | 8 ++++++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 0929554f5a81..2efc33b1cade 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -12,8 +12,8 @@ #include "pcie-cadence.h" -static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, - int where) +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) { struct pci_host_bridge *bridge = pci_find_host_bridge(bus); struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); @@ -289,7 +289,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; bridge->busnr = pcie->bus; - bridge->ops = &cdns_pcie_host_ops; + if (!bridge->ops) + bridge->ops = &cdns_pcie_host_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 5171d0da37da..c879dd3d2893 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -472,11 +472,19 @@ static inline bool cdns_pcie_is_link_up(struct cdns_pcie *pcie) #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); #else static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { return 0; } + +static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, + unsigned int devfn, + int where) +{ +} #endif #ifdef CONFIG_PCIE_CADENCE_EP