From patchwork Tue Mar 3 10:54:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11417715 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7BA6C14B7 for ; Tue, 3 Mar 2020 10:54:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5ADBB2080C for ; Tue, 3 Mar 2020 10:54:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="lY5saZ+c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728934AbgCCKyu (ORCPT ); Tue, 3 Mar 2020 05:54:50 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:1739 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728905AbgCCKyt (ORCPT ); Tue, 3 Mar 2020 05:54:49 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 03 Mar 2020 02:54:35 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 03 Mar 2020 02:54:48 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 03 Mar 2020 02:54:48 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 3 Mar 2020 10:54:48 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 3 Mar 2020 10:54:48 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 03 Mar 2020 02:54:48 -0800 From: Vidya Sagar To: , , , , , CC: , , , , , , , , , , Subject: [PATCH V4 4/5] arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform Date: Tue, 3 Mar 2020 16:24:17 +0530 Message-ID: <20200303105418.2840-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200303105418.2840-1-vidyas@nvidia.com> References: <20200303105418.2840-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1583232875; bh=XDqU4/3NkhzOg4VQyRoeDPrk+BoR8HLjcQcuG2F+Bmw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=lY5saZ+ceeSgf1Ns8Fy/inHT9AHdqSo+oMMKHg/mTZcF4OigepBHEyMCqWo8nlOHi jypbAwUcIvffJgRWxAR5q7YbirP3aPb4XEiJnh+DWRdwlvJH9eEog7y4KjnU85Wv0+ 6OeJCl3G3brTcIKycW4UU9CJ4Kyqa7rzyfTp8oMW7U8Y+6CRtZrWUdmtDAQrtPPjzD HnxPHBQ4eODcaZkEAj2bI41m7NuEQs4ZyoPJphTBe3ydU9+Kftn/sgW7ZDfThTFreQ pO4NPxKddVV44kpL0vFgv5LNm6VBSBmish+Em1b0WAbPlS17/JChS5VG+5p1z5Q7Vm R1oJ4k3huOlpw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add endpoint mode support for PCIe C5 controller in P2972-0000 platform with information about supplies, PHY, PERST GPIO and GPIO that controls PCIe reference clock coming from the host system. Signed-off-by: Vidya Sagar --- V4: * None V3: * None V2: * Addressed Thierry's review comments * Changed 'nvidia,pex-rst-gpio' to 'reset-gpios' * Added 'nvidia,refclk-select-gpios' .../boot/dts/nvidia/tegra194-p2972-0000.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index f9f874d9d0ae..e15d1eac05f5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -199,6 +199,24 @@ "p2u-5", "p2u-6", "p2u-7"; }; + pcie_ep@141a0000 { + status = "disabled"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; + + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) + GPIO_ACTIVE_HIGH>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + fan: fan { compatible = "pwm-fan"; pwms = <&pwm4 0 45334>;