From patchwork Tue Mar 3 13:28:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Spassov X-Patchwork-Id: 11418007 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10C7314B7 for ; Tue, 3 Mar 2020 13:30:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E4B8320842 for ; Tue, 3 Mar 2020 13:30:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b="onAKr0+t" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728850AbgCCNaJ (ORCPT ); Tue, 3 Mar 2020 08:30:09 -0500 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:61587 "EHLO smtp-fw-33001.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728068AbgCCNaJ (ORCPT ); Tue, 3 Mar 2020 08:30:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1583242208; x=1614778208; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7WM9yX1OJkKXJJaN0Bul5znh9nhHO2FbDkre7Td3gO0=; b=onAKr0+ts16dbD2+VkV/undi3EfSN346NAQHhV56k2/qSY6xi9yzm4MI O46QCb5LmCSPhEryy4ZGPDhsQ9yh/cs9CGI322jSEpjnVW+mqft7E4GFk g5HpKEzUICUU5KKRfqO0UxSoNqc1a+m4FTtebd9p3fbwjtnezOPBN61mF I=; IronPort-SDR: mdqZXfd6/iJ+37fvCK9FrLPkkeAsXdUvL1PNWQ85fyeOBxPFqFSXt6UG5vhZxLyjggZVvqa3Ft 4x9mXvfNyDFA== X-IronPort-AV: E=Sophos;i="5.70,511,1574121600"; d="scan'208";a="30249617" Received: from sea32-co-svc-lb4-vlan3.sea.corp.amazon.com (HELO email-inbound-relay-2c-397e131e.us-west-2.amazon.com) ([10.47.23.38]) by smtp-border-fw-out-33001.sea14.amazon.com with ESMTP; 03 Mar 2020 13:30:06 +0000 Received: from EX13MTAUEA002.ant.amazon.com (pdx4-ws-svc-p6-lb7-vlan3.pdx.amazon.com [10.170.41.166]) by email-inbound-relay-2c-397e131e.us-west-2.amazon.com (Postfix) with ESMTPS id E118AA34C5; Tue, 3 Mar 2020 13:30:04 +0000 (UTC) Received: from EX13D12EUA003.ant.amazon.com (10.43.165.147) by EX13MTAUEA002.ant.amazon.com (10.43.61.77) with Microsoft SMTP Server (TLS) id 15.0.1236.3; Tue, 3 Mar 2020 13:29:53 +0000 Received: from EX13MTAUEE002.ant.amazon.com (10.43.62.24) by EX13D12EUA003.ant.amazon.com (10.43.165.147) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Mar 2020 13:29:52 +0000 Received: from u961addbe640f56.ant.amazon.com (10.28.84.111) by mail-relay.amazon.com (10.43.62.224) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Tue, 3 Mar 2020 13:29:49 +0000 From: Stanislav Spassov To: CC: Stanislav Spassov , , Bjorn Helgaas , Thomas Gleixner , Andrew Morton , =?utf-8?q?Jan_H_=2E_Sch=C3=B6nhe?= =?utf-8?q?rr?= , "Jonathan Corbet" , Ashok Raj , Alex Williamson , Sinan Kaya , Rajat Jain , kbuild test robot Subject: [PATCH v3 04/17] PCI: Do not override delay for D0->D3hot transition Date: Tue, 3 Mar 2020 14:28:39 +0100 Message-ID: <20200303132852.13184-5-stanspas@amazon.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200303132852.13184-1-stanspas@amazon.com> References: <20200303132852.13184-1-stanspas@amazon.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Stanislav Spassov Both specifications that document mechanisms for overriding the D3hot->D0 waiting time only speak of this specific direction. Nothing is mentioned about the opposite (D*->D3hot) except for the default value of 10ms in PCI Express Base Specification r5.0 (May 22, 2019), Section 5.9 "State Transition Recovery Time Requirements". Signed-off-by: Stanislav Spassov --- drivers/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c1a866f733e9..03103bb15b42 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4589,7 +4589,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) csr &= ~PCI_PM_CTRL_STATE_MASK; csr |= PCI_D3hot; pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); - pci_dev_d3_sleep(dev); + msleep(PCI_PM_D3_WAIT); csr &= ~PCI_PM_CTRL_STATE_MASK; csr |= PCI_D0;