diff mbox series

[3/3] PCI: Cadence: Remove using "cdns,max-outbound-regions" DT property

Message ID 20200327104727.4708-4-kishon@ti.com
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
Series PCI: cadence: Deprecate inbound/outbound specific bindings | expand

Commit Message

Kishon Vijay Abraham I March 27, 2020, 10:47 a.m. UTC
"cdns,max-outbound-regions" device tree property provides the
maximum number of outbound regions supported by the Host PCIe
controller. However the outbound regions are configured based
on what is populated in the "ranges" DT property.
Avoid using two properties for configuring outbound regions and
use only "ranges" property instead.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-host.c | 6 ------
 drivers/pci/controller/cadence/pcie-cadence.h      | 2 --
 2 files changed, 8 deletions(-)

Comments

Bjorn Helgaas March 27, 2020, 2:54 p.m. UTC | #1
Update subject to match capitalization of others:

  PCI: cadence: Remove "cdns,max-outbound-regions" DT property

On Fri, Mar 27, 2020 at 04:17:27PM +0530, Kishon Vijay Abraham I wrote:
> "cdns,max-outbound-regions" device tree property provides the
> maximum number of outbound regions supported by the Host PCIe
> controller. However the outbound regions are configured based
> on what is populated in the "ranges" DT property.

Looks like this is missing a blank line here?  Or it should be
rewrapped as part of the above paragraph?  I think the below makes
more sense as a separate paragraph, though.

Again, thanks for doing this; this is a great cleanup.

> Avoid using two properties for configuring outbound regions and
> use only "ranges" property instead.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 6 ------
>  drivers/pci/controller/cadence/pcie-cadence.h      | 2 --
>  2 files changed, 8 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 60f912a657b9..8f72967f298f 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -140,9 +140,6 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>  	for_each_of_pci_range(&parser, &range) {
>  		bool is_io;
>  
> -		if (r >= rc->max_regions)
> -			break;
> -
>  		if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
>  			is_io = false;
>  		else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
> @@ -221,9 +218,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
>  	pcie = &rc->pcie;
>  	pcie->is_rc = true;
>  
> -	rc->max_regions = 32;
> -	of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
> -
>  	if (!of_pci_dma_range_parser_init(&parser, np))
>  		if (of_pci_range_parser_one(&parser, &range))
>  			rc->no_bar_nbits = ilog2(range.size);
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index a2b28b912ca4..6bd89a21bb1c 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -251,7 +251,6 @@ struct cdns_pcie {
>   * @bus_range: first/last buses behind the PCIe host controller
>   * @cfg_base: IO mapped window to access the PCI configuration space of a
>   *            single function at a time
> - * @max_regions: maximum number of regions supported by the hardware
>   * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
>   *                translation (nbits sets into the "no BAR match" register)
>   * @vendor_id: PCI vendor ID
> @@ -262,7 +261,6 @@ struct cdns_pcie_rc {
>  	struct resource		*cfg_res;
>  	struct resource		*bus_range;
>  	void __iomem		*cfg_base;
> -	u32			max_regions;
>  	u32			no_bar_nbits;
>  	u16			vendor_id;
>  	u16			device_id;
> -- 
> 2.17.1
>
Kishon Vijay Abraham I March 27, 2020, 3:27 p.m. UTC | #2
Hi Bjorn,

On 3/27/2020 8:24 PM, Bjorn Helgaas wrote:
> Update subject to match capitalization of others:
> 
>   PCI: cadence: Remove "cdns,max-outbound-regions" DT property
> 
> On Fri, Mar 27, 2020 at 04:17:27PM +0530, Kishon Vijay Abraham I wrote:
>> "cdns,max-outbound-regions" device tree property provides the
>> maximum number of outbound regions supported by the Host PCIe
>> controller. However the outbound regions are configured based
>> on what is populated in the "ranges" DT property.
> 
> Looks like this is missing a blank line here?  Or it should be
> rewrapped as part of the above paragraph?  I think the below makes
> more sense as a separate paragraph, though.

I'll add a blank line for the next paragraph and re-post once I get Ack from
Rob on the DT binding patch.

Thanks for reviewing!

Regards
Kishon
> 
> Again, thanks for doing this; this is a great cleanup.
> 
>> Avoid using two properties for configuring outbound regions and
>> use only "ranges" property instead.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  drivers/pci/controller/cadence/pcie-cadence-host.c | 6 ------
>>  drivers/pci/controller/cadence/pcie-cadence.h      | 2 --
>>  2 files changed, 8 deletions(-)
>>
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> index 60f912a657b9..8f72967f298f 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> @@ -140,9 +140,6 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>>  	for_each_of_pci_range(&parser, &range) {
>>  		bool is_io;
>>  
>> -		if (r >= rc->max_regions)
>> -			break;
>> -
>>  		if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
>>  			is_io = false;
>>  		else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
>> @@ -221,9 +218,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
>>  	pcie = &rc->pcie;
>>  	pcie->is_rc = true;
>>  
>> -	rc->max_regions = 32;
>> -	of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
>> -
>>  	if (!of_pci_dma_range_parser_init(&parser, np))
>>  		if (of_pci_range_parser_one(&parser, &range))
>>  			rc->no_bar_nbits = ilog2(range.size);
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
>> index a2b28b912ca4..6bd89a21bb1c 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>> @@ -251,7 +251,6 @@ struct cdns_pcie {
>>   * @bus_range: first/last buses behind the PCIe host controller
>>   * @cfg_base: IO mapped window to access the PCI configuration space of a
>>   *            single function at a time
>> - * @max_regions: maximum number of regions supported by the hardware
>>   * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
>>   *                translation (nbits sets into the "no BAR match" register)
>>   * @vendor_id: PCI vendor ID
>> @@ -262,7 +261,6 @@ struct cdns_pcie_rc {
>>  	struct resource		*cfg_res;
>>  	struct resource		*bus_range;
>>  	void __iomem		*cfg_base;
>> -	u32			max_regions;
>>  	u32			no_bar_nbits;
>>  	u16			vendor_id;
>>  	u16			device_id;
>> -- 
>> 2.17.1
>>
diff mbox series

Patch

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 60f912a657b9..8f72967f298f 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -140,9 +140,6 @@  static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
 	for_each_of_pci_range(&parser, &range) {
 		bool is_io;
 
-		if (r >= rc->max_regions)
-			break;
-
 		if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
 			is_io = false;
 		else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
@@ -221,9 +218,6 @@  int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	pcie = &rc->pcie;
 	pcie->is_rc = true;
 
-	rc->max_regions = 32;
-	of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
-
 	if (!of_pci_dma_range_parser_init(&parser, np))
 		if (of_pci_range_parser_one(&parser, &range))
 			rc->no_bar_nbits = ilog2(range.size);
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index a2b28b912ca4..6bd89a21bb1c 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -251,7 +251,6 @@  struct cdns_pcie {
  * @bus_range: first/last buses behind the PCIe host controller
  * @cfg_base: IO mapped window to access the PCI configuration space of a
  *            single function at a time
- * @max_regions: maximum number of regions supported by the hardware
  * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
  *                translation (nbits sets into the "no BAR match" register)
  * @vendor_id: PCI vendor ID
@@ -262,7 +261,6 @@  struct cdns_pcie_rc {
 	struct resource		*cfg_res;
 	struct resource		*bus_range;
 	void __iomem		*cfg_base;
-	u32			max_regions;
 	u32			no_bar_nbits;
 	u16			vendor_id;
 	u16			device_id;