diff mbox series

[v2,4/4] PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DT

Message ID 20200417114322.31111-5-kishon@ti.com
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
Series PCI: cadence: Deprecate inbound/outbound specific bindings | expand

Commit Message

Kishon Vijay Abraham I April 17, 2020, 11:43 a.m. UTC
The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
defines both Vendor ID and Device ID to be 32-bits. Fix
pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
properties from device tree.

[1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++--
 drivers/pci/controller/cadence/pcie-cadence.h      | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

Comments

Lorenzo Pieralisi May 1, 2020, 3:11 p.m. UTC | #1
On Fri, Apr 17, 2020 at 05:13:22PM +0530, Kishon Vijay Abraham I wrote:
> The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
> defines both Vendor ID and Device ID to be 32-bits. Fix
> pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
> properties from device tree.
> 
> [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++--
>  drivers/pci/controller/cadence/pcie-cadence.h      | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)

I don't see how you would use a 32-bit value for a 16-bit register so
certainly the struct cdns_pcie_rc fields size is questionable anyway.

I *assume* you are referring to 4.1.2.1 and the property list
encoded as "encode-int".

I would like to get RobH's opinion on this - I don't know myself
whether the PCI OF bindings you added are still relevant and how
they should be interpreted.

Thanks
Lorenzo

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 8f72967f298f..31e67c9c88cf 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -229,10 +229,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
>  	}
>  
>  	rc->vendor_id = 0xffff;
> -	of_property_read_u16(np, "vendor-id", &rc->vendor_id);
> +	of_property_read_u32(np, "vendor-id", &rc->vendor_id);
>  
>  	rc->device_id = 0xffff;
> -	of_property_read_u16(np, "device-id", &rc->device_id);
> +	of_property_read_u32(np, "device-id", &rc->device_id);
>  
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
>  	pcie->reg_base = devm_ioremap_resource(dev, res);
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 6bd89a21bb1c..df14ad002fe9 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -262,8 +262,8 @@ struct cdns_pcie_rc {
>  	struct resource		*bus_range;
>  	void __iomem		*cfg_base;
>  	u32			no_bar_nbits;
> -	u16			vendor_id;
> -	u16			device_id;
> +	u32			vendor_id;
> +	u32			device_id;
>  };
>  
>  /**
> -- 
> 2.17.1
>
Kishon Vijay Abraham I May 4, 2020, 8:52 a.m. UTC | #2
Hi Lorenzo,

On 5/1/2020 8:41 PM, Lorenzo Pieralisi wrote:
> On Fri, Apr 17, 2020 at 05:13:22PM +0530, Kishon Vijay Abraham I wrote:
>> The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
>> defines both Vendor ID and Device ID to be 32-bits. Fix
>> pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
>> properties from device tree.
>>
>> [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++--
>>  drivers/pci/controller/cadence/pcie-cadence.h      | 4 ++--
>>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> I don't see how you would use a 32-bit value for a 16-bit register so
> certainly the struct cdns_pcie_rc fields size is questionable anyway.
> 
> I *assume* you are referring to 4.1.2.1 and the property list
> encoded as "encode-int".
> 
> I would like to get RobH's opinion on this - I don't know myself
> whether the PCI OF bindings you added are still relevant and how
> they should be interpreted.

This change was made due to RobH's comment below [1]

[1] ->
https://lore.kernel.org/r/CAL_JsqLYScxGySy8xaN-UB6URfw8K_jSiuSXwVoTU9-RdJecww@mail.gmail.com/

Thanks
Kishon

> 
> Thanks
> Lorenzo
> 
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> index 8f72967f298f..31e67c9c88cf 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> @@ -229,10 +229,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
>>  	}
>>  
>>  	rc->vendor_id = 0xffff;
>> -	of_property_read_u16(np, "vendor-id", &rc->vendor_id);
>> +	of_property_read_u32(np, "vendor-id", &rc->vendor_id);
>>  
>>  	rc->device_id = 0xffff;
>> -	of_property_read_u16(np, "device-id", &rc->device_id);
>> +	of_property_read_u32(np, "device-id", &rc->device_id);
>>  
>>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
>>  	pcie->reg_base = devm_ioremap_resource(dev, res);
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
>> index 6bd89a21bb1c..df14ad002fe9 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>> @@ -262,8 +262,8 @@ struct cdns_pcie_rc {
>>  	struct resource		*bus_range;
>>  	void __iomem		*cfg_base;
>>  	u32			no_bar_nbits;
>> -	u16			vendor_id;
>> -	u16			device_id;
>> +	u32			vendor_id;
>> +	u32			device_id;
>>  };
>>  
>>  /**
>> -- 
>> 2.17.1
>>
Lorenzo Pieralisi May 4, 2020, 11:25 a.m. UTC | #3
On Mon, May 04, 2020 at 02:22:30PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
> 
> On 5/1/2020 8:41 PM, Lorenzo Pieralisi wrote:
> > On Fri, Apr 17, 2020 at 05:13:22PM +0530, Kishon Vijay Abraham I wrote:
> >> The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
> >> defines both Vendor ID and Device ID to be 32-bits. Fix
> >> pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
> >> properties from device tree.
> >>
> >> [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
> >>
> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> ---
> >>  drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++--
> >>  drivers/pci/controller/cadence/pcie-cadence.h      | 4 ++--
> >>  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > I don't see how you would use a 32-bit value for a 16-bit register so
> > certainly the struct cdns_pcie_rc fields size is questionable anyway.
> > 
> > I *assume* you are referring to 4.1.2.1 and the property list
> > encoded as "encode-int".
> > 
> > I would like to get RobH's opinion on this - I don't know myself
> > whether the PCI OF bindings you added are still relevant and how
> > they should be interpreted.
> 
> This change was made due to RobH's comment below [1]
> 
> [1] ->
> https://lore.kernel.org/r/CAL_JsqLYScxGySy8xaN-UB6URfw8K_jSiuSXwVoTU9-RdJecww@mail.gmail.com/

Thanks for the pointer - that's what I needed to proceed with this
patch.

Lorenzo

> Thanks
> Kishon
> 
> > 
> > Thanks
> > Lorenzo
> > 
> >> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> >> index 8f72967f298f..31e67c9c88cf 100644
> >> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> >> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> >> @@ -229,10 +229,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> >>  	}
> >>  
> >>  	rc->vendor_id = 0xffff;
> >> -	of_property_read_u16(np, "vendor-id", &rc->vendor_id);
> >> +	of_property_read_u32(np, "vendor-id", &rc->vendor_id);
> >>  
> >>  	rc->device_id = 0xffff;
> >> -	of_property_read_u16(np, "device-id", &rc->device_id);
> >> +	of_property_read_u32(np, "device-id", &rc->device_id);
> >>  
> >>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> >>  	pcie->reg_base = devm_ioremap_resource(dev, res);
> >> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> >> index 6bd89a21bb1c..df14ad002fe9 100644
> >> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> >> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> >> @@ -262,8 +262,8 @@ struct cdns_pcie_rc {
> >>  	struct resource		*bus_range;
> >>  	void __iomem		*cfg_base;
> >>  	u32			no_bar_nbits;
> >> -	u16			vendor_id;
> >> -	u16			device_id;
> >> +	u32			vendor_id;
> >> +	u32			device_id;
> >>  };
> >>  
> >>  /**
> >> -- 
> >> 2.17.1
> >>
Rob Herring May 7, 2020, 8:27 p.m. UTC | #4
On Fri, 17 Apr 2020 17:13:22 +0530, Kishon Vijay Abraham I wrote:
> The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
> defines both Vendor ID and Device ID to be 32-bits. Fix
> pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
> properties from device tree.
> 
> [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++--
>  drivers/pci/controller/cadence/pcie-cadence.h      | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 8f72967f298f..31e67c9c88cf 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -229,10 +229,10 @@  int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	}
 
 	rc->vendor_id = 0xffff;
-	of_property_read_u16(np, "vendor-id", &rc->vendor_id);
+	of_property_read_u32(np, "vendor-id", &rc->vendor_id);
 
 	rc->device_id = 0xffff;
-	of_property_read_u16(np, "device-id", &rc->device_id);
+	of_property_read_u32(np, "device-id", &rc->device_id);
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
 	pcie->reg_base = devm_ioremap_resource(dev, res);
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 6bd89a21bb1c..df14ad002fe9 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -262,8 +262,8 @@  struct cdns_pcie_rc {
 	struct resource		*bus_range;
 	void __iomem		*cfg_base;
 	u32			no_bar_nbits;
-	u16			vendor_id;
-	u16			device_id;
+	u32			vendor_id;
+	u32			device_id;
 };
 
 /**