From patchwork Thu Sep 10 06:11:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanjia Liu X-Patchwork-Id: 11766691 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09607698 for ; Thu, 10 Sep 2020 06:14:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DEB3120795 for ; Thu, 10 Sep 2020 06:14:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="nTfkAeXk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbgIJGOe (ORCPT ); Thu, 10 Sep 2020 02:14:34 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:23963 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726647AbgIJGOc (ORCPT ); Thu, 10 Sep 2020 02:14:32 -0400 X-UUID: 92366f52c11c49ec8411eb9da262c7df-20200910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xloUjBE6OF+ENLRHth9hL5fNUGfyOv8h8Vtqb+yulXk=; b=nTfkAeXkYYvzFy0uVMmVgpJ6yeJqDAgad8mtu/eppQ4AH3uDiSnxGTifiskLsMbBrPTaCzkdSpsVk6Z4vEEjrKYzTACl/RdrkBPpYmWDdoXWQCeeNeH4YvTwg6H0XWyOQ//5HGKlFr+SVrDld5u4PQoSOObfiq9nPSBF7gWvGH8=; X-UUID: 92366f52c11c49ec8411eb9da262c7df-20200910 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 552507246; Thu, 10 Sep 2020 14:14:27 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Sep 2020 14:14:24 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Sep 2020 14:14:24 +0800 From: Chuanjia Liu To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi CC: , , , , , Frank Wunderlich , Ryder Lee , Chuanjia Liu Subject: [PATCH v5 4/4] ARM: dts: mediatek: Modified MT7629 PCIe node Date: Thu, 10 Sep 2020 14:11:15 +0800 Message-ID: <20200910061115.909-5-chuanjia.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200910061115.909-1-chuanjia.liu@mediatek.com> References: <20200910061115.909-1-chuanjia.liu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 06F033A27D6FEFF1385F1BA824970B003F89F257B2FE2FFDC1AA77B79BE1042B2000:8 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Remove unused property and add pciecfg node. Acked-by: Ryder Lee Signed-off-by: Chuanjia Liu --- arch/arm/boot/dts/mt7629-rfb.dts | 3 ++- arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++---------- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts index 9980c10c6e29..eb536cbebd9b 100644 --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mt7629-rfb.dts @@ -140,9 +140,10 @@ }; }; -&pcie { +&pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; + status = "okay"; }; &pciephy1 { diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi index 5cbb3d244c75..94567307b842 100644 --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi @@ -360,16 +360,21 @@ #reset-cells = <1>; }; - pcie: pcie@1a140000 { + pciecfg: pciecfg@1a140000 { + compatible = "mediatek,mt7629-pciecfg", "syscon"; + reg = <0x1a140000 0x1000>; + }; + + pcie1: pcie@1a145000 { compatible = "mediatek,mt7629-pcie"; device_type = "pci"; - reg = <0x1a140000 0x1000>, - <0x1a145000 0x1000>; - reg-names = "subsys","port1"; + reg = <0x1a145000 0x1000>; + reg-names = "port1"; + mediatek,pcie-cfg = <&pciecfg>; #address-cells = <3>; #size-cells = <2>; - interrupts = , - ; + interrupts = ; + interrupt-names = "pcie_irq"; clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, <&pciesys CLK_PCIE_P0_AHB_EN>, <&pciesys CLK_PCIE_P1_AUX_EN>, @@ -390,21 +395,19 @@ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; + status = "disabled"; - pcie1: pcie@1,0 { - device_type = "pci"; + slot1: pcie@1,0 { reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; ranges; - num-lanes = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, <0 0 0 2 &pcie_intc1 1>, <0 0 0 3 &pcie_intc1 2>, <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { interrupt-controller; #address-cells = <0>;