From patchwork Wed Sep 16 14:57:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 11781015 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD148139F for ; Wed, 16 Sep 2020 21:08:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 709512087D for ; Wed, 16 Sep 2020 21:08:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="SnFiideW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726183AbgIPVIC (ORCPT ); Wed, 16 Sep 2020 17:08:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726466AbgIPQDk (ORCPT ); Wed, 16 Sep 2020 12:03:40 -0400 Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27908C0D942B for ; Wed, 16 Sep 2020 07:57:27 -0700 (PDT) Received: by mail-pl1-x643.google.com with SMTP id j7so3328000plk.11 for ; Wed, 16 Sep 2020 07:57:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1MZwtpdbpR82U6Gt5FPzGRx8447icke/57YKQin/C1w=; b=SnFiideW4v1h1GfuLr0YBWu2m48RxJpZzGlNwB1zlyIT23pDJs4jM3UpJ3BjlCo3Ln 4AchZFaZESPBSmajWtg5TX/E8D0adUngXBLnB2hy8JFX+PS/xC8KI0i66fWhMyjbVRoA drnFWt+5AVxOoeMbV94rHALapPtenW82hv1n4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1MZwtpdbpR82U6Gt5FPzGRx8447icke/57YKQin/C1w=; b=HDF8hZqiPGmqt6HQ+wSpb7vYjs5EnJnZUfl8YNmWpsJWGiF1OWHPcZot6UwJpxav0z fNoIQ7HItpGr/RzCaBjxrQz+u1G4d19dQRZPRoXHyou4X7qgBCrkvab/BvP9au1NVj8Q TUz9YMXvkj46qjEjhIMP8hGtu8IZQvyM2IbKTnhnLEXZygbDsxKJ3AteMPefZpSNfZpo SccUnCptiy+TZ3b3nITKj10KnLUBFd9pC3Nm1LYD5Mcfzt6JHLhm6YQhKc8XMa3z6gJ5 VEWS0ETyNi4NYTrxStk/oxwqs6/IkoB7iIEysnmCHLT4TD1PV8+kyBvdab8KltwOFy4K BbQg== X-Gm-Message-State: AOAM532IVtDjiZqiFf9qBtflpswJKeq4s9a8QoFpHGAndXswskyUNar0 l9uytS120hGUFHb8jdJRgSFisKFWHvdTw0SrixH5WAuB58HgoeHqa7okPF09t8cFKwEJy7u68aS bdUODgZ3h4xmgJfwge0X4R+8VcqJxoXSTVQMxIujkaHkZluA8vziuqWl/dqa6N8k7yMjPyKTbfI r+Txeg X-Google-Smtp-Source: ABdhPJxPdcFIJf7Y7r7V+T6n57+3CMecgJqMly75nRv6uxltu3DUIVK67DoStHARIsYQ7H1Y9yQx+g== X-Received: by 2002:a17:902:7844:b029:d0:cbe1:e704 with SMTP id e4-20020a1709027844b02900d0cbe1e704mr24389033pln.18.1600268246713; Wed, 16 Sep 2020 07:57:26 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id 82sm15070257pgd.6.2020.09.16.07.57.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2020 07:57:26 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Bjorn Helgaas , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/1] PCI: pcie_bus_config can be set at build time Date: Wed, 16 Sep 2020 10:57:06 -0400 Message-Id: <20200916145707.33313-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200916145707.33313-1-james.quinlan@broadcom.com> References: <20200916145707.33313-1-james.quinlan@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Kconfig is modified so that the pcie_bus_config setting can be done at build time in the same manner as the CONFIG_PCIEASPM_XXXX choice. The pci_bus_config setting may still be overridden by the bootline param. Signed-off-by: Jim Quinlan --- drivers/pci/Kconfig | 56 +++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.c | 12 ++++++++++ 2 files changed, 68 insertions(+) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 4bef5c2bae9f..15ce948858fb 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -187,6 +187,62 @@ config PCI_HYPERV The PCI device frontend driver allows the kernel to import arbitrary PCI devices from a PCI backend to support PCI driver domains. +choice + prompt "PCIE default bus config setting" + default PCIE_BUS_DEFAULT + depends on PCI + help + One of the following choices will set the pci_bus_config at + compile time. The choices offered are the same as those offered + for the bootline parameter 'pci'; i.e. 'pci=pcie_bus_tune_off', + 'pci=pcie_bus_safe', 'pci=pcie_bus_perf', and 'pci=pcie_bus_peer2peer'. + This is a compile-time setting and is still be overridden by the + above bootline parameters, if present. If unsure, chose PCIE_BUS_DEFAULT. + +config PCIE_BUS_TUNE_OFF + bool "Tune Off" + depends on PCI + help + Use the BIOS defaults; doesn't touch MPS at all. This is the same + as booting with 'pci=pcie_bus_tune_off'. + +config PCIE_BUS_DEFAULT + bool "Default" + depends on PCI + help + Default choice; ensures that the MPS matches upstream bridge. + +config PCIE_BUS_SAFE + bool "Safe" + depends on PCI + help + Use largest MPS that boot-time devices support. If you have a + closed system with no possibility of adding new devices, + this will use the largest MPS that's supported by all devices. + This is the same as booting with 'pci=pcie_bus_safe'. + +config PCIE_BUS_PERFORMANCE + bool "Performance" + depends on PCI + help + Use MPS and MRRS for best performance. This setting ensures + that a given device's MPS is no larger than its parent MPS, + which allows us to keep all switches/bridges to the max MPS supported + by their parent and eventually the PHB. This is the same as + booting with 'pci=pcie_bus_perf'. + +config PCIE_BUS_PEER2PEER + bool "Peer2peer" + depends on PCI + help + Set MPS = 128 for all devices. MPS configuration effected by + the other options could cause the MPS on one root port to be + different than that of the MPS on another. Simply making the system + wide MPS be set to the smallest possible value (128B) solves + this issue. This is the same as booting with 'pci=pcie_bus_peer2peer'. + +endchoice + source "drivers/pci/hotplug/Kconfig" source "drivers/pci/controller/Kconfig" source "drivers/pci/endpoint/Kconfig" diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e39c5499770f..dfb52ed4a931 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -101,7 +101,19 @@ unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE; #define DEFAULT_HOTPLUG_BUS_SIZE 1 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; + +/* PCIE bus config, can be overridden by bootline param */ +#ifdef CONFIG_PCIE_BUS_TUNE_OFF +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; +#elif defined CONFIG_PCIE_BUS_SAFE +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE; +#elif defined CONFIG_PCIE_BUS_PERFORMANCE +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE; +#elif defined CONFIG_PCIE_BUS_PEER2PEER +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER; +#else enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; +#endif /* * The default CLS is used if arch didn't set CLS explicitly and not