From patchwork Mon Sep 28 19:46:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 11804583 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C68992C for ; Mon, 28 Sep 2020 19:47:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6502A2078B for ; Mon, 28 Sep 2020 19:47:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="ITLxxLwS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726727AbgI1Tq7 (ORCPT ); Mon, 28 Sep 2020 15:46:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726692AbgI1Tq7 (ORCPT ); Mon, 28 Sep 2020 15:46:59 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09F9BC061755 for ; Mon, 28 Sep 2020 12:46:59 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id bw23so1297242pjb.2 for ; Mon, 28 Sep 2020 12:46:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9HP7gcDntO/V+LNMKR4T3K88zhtdehTMMmU7iOInnY8=; b=ITLxxLwSh53UyzuRRRJfcNzHb4NsDQOg+xT7GFCIjtCA3XXYO5XbGsQEn53uXKyasB qDIBNdah6BFCalr/g3xaNuLkE/QRmo1rq9xyz90mKBrJAWYg3H3vcpAMH0CUTuptH9AP 5H/+//Sl/1B+ye1o1ZggUakiyE1NQvkYTCPtA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9HP7gcDntO/V+LNMKR4T3K88zhtdehTMMmU7iOInnY8=; b=Kqy7uFan+clZ3Ac7N00kG1+ov6VVlkUQMM6fVfUYuY5YV01nAd8x3Y7ApUP3pbcuas 2yNPbm0wIBODfYD5g3Nihsm0JfT79oA0fk7jBmC547YH9kw9pzP1333nBiGISsWG3mMq NXC+iSv1UBho9slJRIknQzYVIVAoMibqRZbBvQ7aS4cTa2aZHcYDDpLX2UorPsYdhOET dZGA8rWEOBhFqFf7dTsP16kM/p+ZSrB0uCwnMpHzXa7ap9dsf6ky8pHDAiN8lRq+Ghx+ kYLfwmT6Q47aAFu54kbPbM3tbz6BvUyZo/Z8yq6kiE2lTx5ogB/ohl7wymjPOWIgubCk xSgA== X-Gm-Message-State: AOAM533OEko890uneP69jVnJAVnp8RdgyAEVNIHc4619UjgHWfzxZm23 oLh4oqXKbSSuLaZCZNWmuklp2ZrGSekGdSc6ENygOIMQ9i1JC31/LM6hD5Kj5VQt9QoGbanogRk lUkIp4nedqtofEg30btrQvpKLRvp6wnCNtBz2EYo4mlESIMncwxK4LetpOZpjBo5vZwAQ9zmNQ9 K5JaMf X-Google-Smtp-Source: ABdhPJzu4BH4Um9afVlp1pnRqV0zVTaN42oFwtjPtNoJlPA7xIfRN9Ltv028b/nrv+tmuV3M2a5vMw== X-Received: by 2002:a17:90b:3444:: with SMTP id lj4mr707481pjb.78.1601322417717; Mon, 28 Sep 2020 12:46:57 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id z18sm2506074pfn.186.2020.09.28.12.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2020 12:46:56 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Bjorn Helgaas , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 RESEND 1/1] PCI: pcie_bus_config can be set at build time Date: Mon, 28 Sep 2020 15:46:51 -0400 Message-Id: <20200928194651.5393-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200928194651.5393-1-james.quinlan@broadcom.com> References: <20200928194651.5393-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Kconfig is modified so that the pcie_bus_config setting can be done at build time in the same manner as the CONFIG_PCIEASPM_XXXX choice. The pci_bus_config setting may still be overridden by the bootline param. Signed-off-by: Jim Quinlan --- drivers/pci/Kconfig | 56 +++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.c | 12 ++++++++++ 2 files changed, 68 insertions(+) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 4bef5c2bae9f..15ce948858fb 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -187,6 +187,62 @@ config PCI_HYPERV The PCI device frontend driver allows the kernel to import arbitrary PCI devices from a PCI backend to support PCI driver domains. +choice + prompt "PCIE default bus config setting" + default PCIE_BUS_DEFAULT + depends on PCI + help + One of the following choices will set the pci_bus_config at + compile time. The choices offered are the same as those offered + for the bootline parameter 'pci'; i.e. 'pci=pcie_bus_tune_off', + 'pci=pcie_bus_safe', 'pci=pcie_bus_perf', and 'pci=pcie_bus_peer2peer'. + This is a compile-time setting and is still be overridden by the + above bootline parameters, if present. If unsure, chose PCIE_BUS_DEFAULT. + +config PCIE_BUS_TUNE_OFF + bool "Tune Off" + depends on PCI + help + Use the BIOS defaults; doesn't touch MPS at all. This is the same + as booting with 'pci=pcie_bus_tune_off'. + +config PCIE_BUS_DEFAULT + bool "Default" + depends on PCI + help + Default choice; ensures that the MPS matches upstream bridge. + +config PCIE_BUS_SAFE + bool "Safe" + depends on PCI + help + Use largest MPS that boot-time devices support. If you have a + closed system with no possibility of adding new devices, + this will use the largest MPS that's supported by all devices. + This is the same as booting with 'pci=pcie_bus_safe'. + +config PCIE_BUS_PERFORMANCE + bool "Performance" + depends on PCI + help + Use MPS and MRRS for best performance. This setting ensures + that a given device's MPS is no larger than its parent MPS, + which allows us to keep all switches/bridges to the max MPS supported + by their parent and eventually the PHB. This is the same as + booting with 'pci=pcie_bus_perf'. + +config PCIE_BUS_PEER2PEER + bool "Peer2peer" + depends on PCI + help + Set MPS = 128 for all devices. MPS configuration effected by + the other options could cause the MPS on one root port to be + different than that of the MPS on another. Simply making the system + wide MPS be set to the smallest possible value (128B) solves + this issue. This is the same as booting with 'pci=pcie_bus_peer2peer'. + +endchoice + source "drivers/pci/hotplug/Kconfig" source "drivers/pci/controller/Kconfig" source "drivers/pci/endpoint/Kconfig" diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e39c5499770f..dfb52ed4a931 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -101,7 +101,19 @@ unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE; #define DEFAULT_HOTPLUG_BUS_SIZE 1 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; + +/* PCIE bus config, can be overridden by bootline param */ +#ifdef CONFIG_PCIE_BUS_TUNE_OFF +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; +#elif defined CONFIG_PCIE_BUS_SAFE +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE; +#elif defined CONFIG_PCIE_BUS_PERFORMANCE +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE; +#elif defined CONFIG_PCIE_BUS_PEER2PEER +enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER; +#else enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; +#endif /* * The default CLS is used if arch didn't set CLS explicitly and not