diff --git a/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
new file mode 100644
index 000000000000..11962c205744
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel Keem Bay PCIe EP controller
+
+maintainers:
+  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+properties:
+  compatible:
+      const: intel,keembay-pcie-ep
+
+  reg:
+    items:
+      - description: DesignWare PCIe registers
+      - description: PCIe configuration space
+      - description: Keem Bay specific registers
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: addr_space
+      - const: apb
+
+  interrupts:
+    items:
+      - description: PCIe interrupt
+      - description: PCIe event interrupt
+      - description: PCIe error interrupt
+      - description: PCIe memory access interrupt
+
+  interrupt-names:
+    items:
+      - const: intr
+      - const: ev_intr
+      - const: err_intr
+      - const: mem_access_intr
+
+  num-ib-windows:
+    description: Number of inbound address translation windows
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  num-ob-windows:
+    description: Number of outbound address translation windows
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  num-lanes:
+    description: Number of lanes to use.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 1, 2, 4, 8 ]
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - num-ib-windows
+  - num-ob-windows
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+  - |
+    pcie-ep@37000000 {
+          compatible = "intel,keembay-pcie-ep";
+          reg = <0x37000000 0x00800000>,
+                <0x36000000 0x01000000>,
+                <0x37800000 0x00000200>;
+          reg-names = "dbi", "addr_space", "apb";
+          interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
+                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+          interrupt-names = "intr", "ev_intr", "err_intr",
+                       "mem_access_intr";
+          num-ib-windows = <4>;
+          num-ob-windows = <4>;
+          num-lanes = <2>;
+    };
diff --git a/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
new file mode 100644
index 000000000000..49e5d3d35bd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel Keem Bay PCIe RC controller
+
+maintainers:
+  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+      const: intel,keembay-pcie
+
+  device_type:
+    const: pci
+
+  "#address-cells":
+    const: 3
+
+  "#size-cells":
+    const: 2
+
+  ranges:
+    maxItems: 1
+
+  reset-gpios:
+    maxItems: 1
+
+  reg:
+    items:
+      - description: DesignWare PCIe registers
+      - description: PCIe configuration space
+      - description: Keem Bay specific registers
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: config
+      - const: apb
+
+  clocks:
+    items:
+      - description: bus clock
+      - description: auxiliary clock
+
+  clock-names:
+    items:
+      - const: master
+      - const: aux
+
+  interrupts:
+    items:
+      - description: PCIe interrupt
+      - description: PCIe event interrupt
+      - description: PCIe error interrupt
+
+  interrupt-names:
+    items:
+      - const: intr
+      - const: ev_intr
+      - const: err_intr
+
+  num-lanes:
+    description: Number of lanes to use.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 1, 2, 4, 8 ]
+
+  num-viewport:
+    description: Number of view ports configured in hardware.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 2
+
+required:
+  - compatible
+  - device_type
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - reg-names
+  - ranges
+  - clocks
+  - interrupts
+  - interrupt-names
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #define KEEM_BAY_A53_PCIE
+    #define KEEM_BAY_A53_AUX_PCIE
+    pcie@37000000 {
+          compatible = "intel,keembay-pcie";
+          reg = <0x37000000 0x00800000>,
+                <0x36e00000 0x00200000>,
+                <0x37800000 0x00000200>;
+          reg-names = "dbi", "config", "apb";
+          #address-cells = <3>;
+          #size-cells = <2>;
+          device_type = "pci";
+          ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
+          interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+          interrupt-names = "intr", "ev_intr", "err_intr";
+          clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
+                   <&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
+          clock-names = "master", "aux";
+          reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
+          num-viewport = <4>;
+          num-lanes = <2>;
+    };
