From patchwork Thu Oct 29 08:15:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanjia Liu X-Patchwork-Id: 11865637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CBAA192C for ; Thu, 29 Oct 2020 08:15:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F7002076E for ; Thu, 29 Oct 2020 08:15:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ChLnOLZz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728337AbgJ2IPr (ORCPT ); Thu, 29 Oct 2020 04:15:47 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:53487 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728510AbgJ2IPp (ORCPT ); Thu, 29 Oct 2020 04:15:45 -0400 X-UUID: d13f7f1ea5144932abb169e0728117cb-20201029 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=XMZxyn6b3FBsdxBCB2TKGC6CA3eMv9x5H8CXbCfu32I=; b=ChLnOLZzD98Hv8XXA3ysYu4RDa1fNXWBgT6eZRRCDit9USmq2B/wnqVjSlCcAuQS/sw+2G8nK/DlBkDhfpqFxul87xhBVO1pyqJqlJ57Nir57fB9CX66ilLxCBsaLPDxcOHKLQiH1kawqCvYwhElmES+B95wv1D9DIi/omr5iYY=; X-UUID: d13f7f1ea5144932abb169e0728117cb-20201029 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1601999279; Thu, 29 Oct 2020 16:15:34 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Oct 2020 16:15:31 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 29 Oct 2020 16:15:31 +0800 From: Chuanjia Liu To: Rob Herring , Lorenzo Pieralisi CC: Bjorn Helgaas , Matthias Brugger , , , , , , Frank Wunderlich , Ryder Lee , Subject: [PATCH v7 2/4] PCI: mediatek: Add new method to get shared pcie-cfg base and irq Date: Thu, 29 Oct 2020 16:15:11 +0800 Message-ID: <20201029081513.10562-3-chuanjia.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201029081513.10562-1-chuanjia.liu@mediatek.com> References: <20201029081513.10562-1-chuanjia.liu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 9C279CAB933F5525C2B98DF3722B1F281CCCD40D526927B3E7820706685DC4622000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add new method to get shared pcie-cfg base and pcie irq for new dts format. Signed-off-by: Chuanjia Liu Acked-by: Ryder Lee --- drivers/pci/controller/pcie-mediatek.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index cf4c18f0c25a..5b915eb0cf1e 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -205,6 +207,7 @@ struct mtk_pcie_port { * struct mtk_pcie - PCIe host information * @dev: pointer to PCIe device * @base: IO mapped register base + * @cfg: IO mapped register map for PCIe config * @free_ck: free-run reference clock * @mem: non-prefetchable memory resource * @ports: pointer to PCIe port information @@ -213,6 +216,7 @@ struct mtk_pcie_port { struct mtk_pcie { struct device *dev; void __iomem *base; + struct regmap *cfg; struct clk *free_ck; struct list_head ports; @@ -648,7 +652,11 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, return err; } - port->irq = platform_get_irq(pdev, port->slot); + if (of_find_property(dev->of_node, "interrupt-names", NULL)) + port->irq = platform_get_irq_byname(pdev, "pcie_irq"); + else + port->irq = platform_get_irq(pdev, port->slot); + if (port->irq < 0) return port->irq; @@ -680,6 +688,10 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val |= PCIE_CSR_LTSSM_EN(port->slot) | PCIE_CSR_ASPM_L1_EN(port->slot); writel(val, pcie->base + PCIE_SYS_CFG_V2); + } else if (pcie->cfg) { + val = PCIE_CSR_LTSSM_EN(port->slot) | + PCIE_CSR_ASPM_L1_EN(port->slot); + regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); } /* Assert all reset signals */ @@ -983,6 +995,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); struct resource *regs; + struct device_node *cfg_node; int err; /* get shared registers, which are optional */ @@ -995,6 +1008,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) } } + cfg_node = of_find_compatible_node(NULL, NULL, + "mediatek,generic-pciecfg"); + if (cfg_node) { + pcie->cfg = syscon_node_to_regmap(cfg_node); + if (IS_ERR(pcie->cfg)) + return PTR_ERR(pcie->cfg); + } + pcie->free_ck = devm_clk_get(dev, "free_ck"); if (IS_ERR(pcie->free_ck)) { if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)