diff mbox series

[1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument

Message ID 20201116173141.31873-2-kishon@ti.com (mailing list archive)
State Superseded
Headers show
Series PCI: J721E: Fix Broken DT w.r.t SYSCON DT | expand

Commit Message

Kishon Vijay Abraham I Nov. 16, 2020, 5:31 p.m. UTC
Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
argument. The argument is the register offset within "syscon" used to
configure PCIe controller.

Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
 .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
 2 files changed, 16 insertions(+), 8 deletions(-)

Comments

Rob Herring Nov. 18, 2020, 9:11 p.m. UTC | #1
On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
> argument. The argument is the register offset within "syscon" used to
> configure PCIe controller.
> 
> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: Link: ?

AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 
Link would be okay though.

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>  2 files changed, 16 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> @@ -29,9 +29,13 @@ properties:
>        - const: mem
>  
>    ti,syscon-pcie-ctrl:
> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
> -                 and link speed.
> -    $ref: /schemas/types.yaml#/definitions/phandle
> +    allOf:

You no longer need allOf here.

> +      - $ref: /schemas/types.yaml#/definitions/phandle-array
> +      - items:
> +          - items:
> +            - description: Phandle to the SYSCON entry
> +            - description: pcie_ctrl register offset within SYSCON
> +    description: Specifier for configuring PCIe mode and link speed.
>  
>    power-domains:
>      maxItems: 1
> @@ -80,7 +84,7 @@ examples:
>                   <0x00 0x0d000000 0x00 0x00800000>,
>                   <0x00 0x10000000 0x00 0x08000000>;
>             reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> -           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
> +           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
>             max-link-speed = <3>;
>             num-lanes = <2>;
>             power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> index ee7a8eade3f6..a3b82992bcfa 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> @@ -29,9 +29,13 @@ properties:
>        - const: cfg
>  
>    ti,syscon-pcie-ctrl:
> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
> -      and link speed.
> -    $ref: /schemas/types.yaml#/definitions/phandle
> +    allOf:
> +      - $ref: /schemas/types.yaml#/definitions/phandle-array
> +      - items:
> +          - items:
> +            - description: Phandle to the SYSCON entry
> +            - description: pcie_ctrl register offset within SYSCON
> +    description: Specifier for configuring PCIe mode and link speed.
>  
>    power-domains:
>      maxItems: 1
> @@ -90,7 +94,7 @@ examples:
>                    <0x00 0x0d000000 0x00 0x00800000>,
>                    <0x00 0x10000000 0x00 0x00001000>;
>              reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> -            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
> +            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
>              max-link-speed = <3>;
>              num-lanes = <2>;
>              power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> -- 
> 2.17.1
>
Rob Herring Nov. 19, 2020, 1:41 p.m. UTC | #2
On Mon, 16 Nov 2020 23:01:39 +0530, Kishon Vijay Abraham I wrote:
> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
> argument. The argument is the register offset within "syscon" used to
> configure PCIe controller.
> 
> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>  2 files changed, 16 insertions(+), 8 deletions(-)
> 


My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:36:13: [warning] wrong indentation: expected 14 but found 12 (indentation)
./Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml:36:13: [warning] wrong indentation: expected 14 but found 12 (indentation)

dtschema/dtc warnings/errors:


See https://patchwork.ozlabs.org/patch/1401067

The base for the patch is generally the last rc1. Any dependencies
should be noted.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Kishon Vijay Abraham I Nov. 20, 2020, 5:09 a.m. UTC | #3
Hi Rob,

On 19/11/20 2:41 am, Rob Herring wrote:
> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
>> argument. The argument is the register offset within "syscon" used to
>> configure PCIe controller.
>>
>> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
> 
> Link: Link: ?
> 
> AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 
> Link would be okay though.

Two Links was a typo, will fix it in the next revision. Nishanth as well
was asking about using "Link:" tag for a mailing list discussion.

I started using it after Lorenzo had asked me to use Link tag for
mailing list discussion here sometime back.

https://patchwork.kernel.org/project/linux-pci/patch/20171219083627.7904-1-kishon@ti.com/#21350261

> 
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>>  2 files changed, 16 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> @@ -29,9 +29,13 @@ properties:
>>        - const: mem
>>  
>>    ti,syscon-pcie-ctrl:
>> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
>> -                 and link speed.
>> -    $ref: /schemas/types.yaml#/definitions/phandle
>> +    allOf:
> 
> You no longer need allOf here.

hmm, don't we need it for specifying phandle with fixed cells? FWIW, I
was referring

https://github.com/devicetree-org/dt-schema/blob/master/test/schemas/good-example.yaml#L187

Thank You,
Kishon
Kishon Vijay Abraham I Nov. 26, 2020, 12:53 p.m. UTC | #4
Hi Rob,

On 20/11/20 10:39 am, Kishon Vijay Abraham I wrote:
> Hi Rob,
> 
> On 19/11/20 2:41 am, Rob Herring wrote:
>> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
>>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
>>> argument. The argument is the register offset within "syscon" used to
>>> configure PCIe controller.
>>>
>>> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
>>
>> Link: Link: ?
>>
>> AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 
>> Link would be okay though.
> 
> Two Links was a typo, will fix it in the next revision. Nishanth as well
> was asking about using "Link:" tag for a mailing list discussion.
> 
> I started using it after Lorenzo had asked me to use Link tag for
> mailing list discussion here sometime back.
> 
> https://patchwork.kernel.org/project/linux-pci/patch/20171219083627.7904-1-kishon@ti.com/#21350261
> 
>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> ---
>>>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
>>>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
>>>  2 files changed, 16 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>>> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
>>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>>> @@ -29,9 +29,13 @@ properties:
>>>        - const: mem
>>>  
>>>    ti,syscon-pcie-ctrl:
>>> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
>>> -                 and link speed.
>>> -    $ref: /schemas/types.yaml#/definitions/phandle
>>> +    allOf:
>>
>> You no longer need allOf here.
> 
> hmm, don't we need it for specifying phandle with fixed cells? FWIW, I
> was referring
> 
> https://github.com/devicetree-org/dt-schema/blob/master/test/schemas/good-example.yaml#L187

Can you clarify this please?

Thank You,
Kishon
Rob Herring Nov. 30, 2020, 4:12 p.m. UTC | #5
On Thu, Nov 26, 2020 at 5:53 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Hi Rob,
>
> On 20/11/20 10:39 am, Kishon Vijay Abraham I wrote:
> > Hi Rob,
> >
> > On 19/11/20 2:41 am, Rob Herring wrote:
> >> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
> >>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
> >>> argument. The argument is the register offset within "syscon" used to
> >>> configure PCIe controller.
> >>>
> >>> Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
> >>
> >> Link: Link: ?
> >>
> >> AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1
> >> Link would be okay though.
> >
> > Two Links was a typo, will fix it in the next revision. Nishanth as well
> > was asking about using "Link:" tag for a mailing list discussion.
> >
> > I started using it after Lorenzo had asked me to use Link tag for
> > mailing list discussion here sometime back.
> >
> > https://patchwork.kernel.org/project/linux-pci/patch/20171219083627.7904-1-kishon@ti.com/#21350261
> >
> >>
> >>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >>> ---
> >>>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml     | 12 ++++++++----
> >>>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml   | 12 ++++++++----
> >>>  2 files changed, 16 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> >>> index 3ae3e1a2d4b0..e9685c0bdc3e 100644
> >>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> >>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> >>> @@ -29,9 +29,13 @@ properties:
> >>>        - const: mem
> >>>
> >>>    ti,syscon-pcie-ctrl:
> >>> -    description: Phandle to the SYSCON entry required for configuring PCIe mode
> >>> -                 and link speed.
> >>> -    $ref: /schemas/types.yaml#/definitions/phandle
> >>> +    allOf:
> >>
> >> You no longer need allOf here.
> >
> > hmm, don't we need it for specifying phandle with fixed cells? FWIW, I
> > was referring
> >
> > https://github.com/devicetree-org/dt-schema/blob/master/test/schemas/good-example.yaml#L187
>
> Can you clarify this please?

We are now using json-schema v2019.09 syntax which doesn't ignore
keywords in addition to a $ref as draft7 and earlier did. The old way
with 'allOf' still works though. I just haven't updated the above test
cases.

Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 3ae3e1a2d4b0..e9685c0bdc3e 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -29,9 +29,13 @@  properties:
       - const: mem
 
   ti,syscon-pcie-ctrl:
-    description: Phandle to the SYSCON entry required for configuring PCIe mode
-                 and link speed.
-    $ref: /schemas/types.yaml#/definitions/phandle
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle-array
+      - items:
+          - items:
+            - description: Phandle to the SYSCON entry
+            - description: pcie_ctrl register offset within SYSCON
+    description: Specifier for configuring PCIe mode and link speed.
 
   power-domains:
     maxItems: 1
@@ -80,7 +84,7 @@  examples:
                  <0x00 0x0d000000 0x00 0x00800000>,
                  <0x00 0x10000000 0x00 0x08000000>;
            reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
            max-link-speed = <3>;
            num-lanes = <2>;
            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index ee7a8eade3f6..a3b82992bcfa 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -29,9 +29,13 @@  properties:
       - const: cfg
 
   ti,syscon-pcie-ctrl:
-    description: Phandle to the SYSCON entry required for configuring PCIe mode
-      and link speed.
-    $ref: /schemas/types.yaml#/definitions/phandle
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle-array
+      - items:
+          - items:
+            - description: Phandle to the SYSCON entry
+            - description: pcie_ctrl register offset within SYSCON
+    description: Specifier for configuring PCIe mode and link speed.
 
   power-domains:
     maxItems: 1
@@ -90,7 +94,7 @@  examples:
                   <0x00 0x0d000000 0x00 0x00800000>,
                   <0x00 0x10000000 0x00 0x00001000>;
             reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
             max-link-speed = <3>;
             num-lanes = <2>;
             power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;