From patchwork Thu Dec 3 18:51:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 11949389 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BAEEC18E57 for ; Thu, 3 Dec 2020 18:52:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 14BB4207B8 for ; Thu, 3 Dec 2020 18:52:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731721AbgLCSwG (ORCPT ); Thu, 3 Dec 2020 13:52:06 -0500 Received: from mail.kernel.org ([198.145.29.99]:33364 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731716AbgLCSwG (ORCPT ); Thu, 3 Dec 2020 13:52:06 -0500 From: Bjorn Helgaas Authentication-Results: mail.kernel.org; dkim=permerror (bad message/signature format) To: Vidya Sagar Cc: Lorenzo Pieralisi , Thierry Reding , Jonathan Hunter , Krishna Kishore , Manikanta Maddireddy , Vidya Sagar , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 3/3] PCI/MSI: Set device flag indicating only 32-bit MSI support Date: Thu, 3 Dec 2020 12:51:10 -0600 Message-Id: <20201203185110.1583077-4-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201203185110.1583077-1-helgaas@kernel.org> References: <20201203185110.1583077-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Vidya Sagar The MSI-X Capability requires devices to support 64-bit Message Addresses, but the MSI Capability can support either 32- or 64-bit addresses. Previously, we set dev->no_64bit_msi for a few broken devices that advertise 64-bit MSI support but don't correctly support it. In addition, check the MSI "64-bit Address Capable" bit for all devices and set dev->no_64bit_msi for devices that don't advertise 64-bit support. This allows msi_verify_entries() to catch arch code defects that assign 64-bit addresses when they're not supported. [bhelgaas: set no_64bit_msi in pci_msi_init(), commit log] Link: https://lore.kernel.org/r/20201124105035.24573-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar Signed-off-by: Bjorn Helgaas Reviewed-by: Thierry Reding --- drivers/pci/msi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 3e302ca8a96f..29baa81e7be9 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -623,11 +623,11 @@ static int msi_verify_entries(struct pci_dev *dev) struct msi_desc *entry; for_each_pci_msi_entry(entry, dev) { - if (!dev->no_64bit_msi || !entry->msg.address_hi) - continue; - pci_err(dev, "Device has broken 64-bit MSI but arch" - " tried to assign one above 4G\n"); - return -EIO; + if (entry->msg.address_hi && dev->no_64bit_msi) { + pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", + entry->msg.address_hi, entry->msg.address_lo); + return -EIO; + } } return 0; } @@ -1619,6 +1619,9 @@ void pci_msi_init(struct pci_dev *dev) if (ctrl & PCI_MSI_FLAGS_ENABLE) pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, ctrl & ~PCI_MSI_FLAGS_ENABLE); + + if (!(ctrl & PCI_MSI_FLAGS_64BIT)) + dev->no_64bit_msi = 1; } void pci_msix_init(struct pci_dev *dev)