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Fri, 30 Apr 2021 23:26:48 +0000 Received: from SDONTHINENI-DESKTOP.nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Apr 2021 23:26:46 +0000 From: Shanker Donthineni To: Alex Williamson CC: Bjorn Helgaas , , , Sinan Kaya , Vikram Sethi , Amey Narkhede , "Shanker Donthineni" Subject: [PATCH v5 2/2] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs Date: Fri, 30 Apr 2021 18:26:24 -0500 Message-ID: <20210430232624.25153-2-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430232624.25153-1-sdonthineni@nvidia.com> References: <20210430232624.25153-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 590d81fc-5e8a-49b5-b8c7-08d90c2f6d8b X-MS-TrafficTypeDiagnostic: SA0PR12MB4525: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 23:26:48.8806 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 590d81fc-5e8a-49b5-b8c7-08d90c2f6d8b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4525 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On select platforms, some Nvidia GPU devices do not work with SBR. Triggering SBR would leave the device inoperable for the current system boot. It requires a system hard-reboot to get the GPU device back to normal operating condition post-SBR. For the affected devices, enable NO_BUS_RESET quirk to fix the issue. This issue will be fixed in the next generation of hardware. Signed-off-by: Shanker Donthineni Reviewed-by: Sinan Kaya --- Changes since v4: - Move reset quirk next to the existing no_bus reset quirks Changes since v1: - Split patch into 2, code for handling _RST and SBR specific quirk - The RST based reset is called as a first-class mechanism in the reset code path drivers/pci/quirks.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 8f47d139c381..ceec67342365 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3558,6 +3558,18 @@ static void quirk_no_bus_reset(struct pci_dev *dev) dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; } +/* + * Some Nvidia GPU devices do not work with bus reset, SBR needs to be + * prevented for those affected devices. + */ +static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) +{ + if ((dev->device & 0xffc0) == 0x2340) + quirk_no_bus_reset(dev); +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + /* * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. * The device will throw a Link Down error on AER-capable systems and