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Thu, 27 May 2021 07:46:43 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 00:46:42 -0700 Received: from buildserver-hdc-comms.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 May 2021 00:46:39 -0700 From: Om Prakash Singh To: , , , , CC: , , , , , Om Prakash Singh Subject: [PATCH V1 1/5] PCI: tegra: Fix handling BME_CHGED event Date: Thu, 27 May 2021 13:16:10 +0530 Message-ID: <20210527074614.49149-4-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527074614.49149-1-omp@nvidia.com> References: <20210527074614.49149-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4e04e43d-4d52-443b-24b5-08d920e3925e X-MS-TrafficTypeDiagnostic: BY5PR12MB3892: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2021 07:46:43.3195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e04e43d-4d52-443b-24b5-08d920e3925e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3892 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches "if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct. Signed-off-by: Om Prakash Singh --- drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index bafd2c6ab3c2..c51d666c9d87 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -615,10 +615,10 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) struct tegra_pcie_dw *pcie = arg; struct dw_pcie_ep *ep = &pcie->pci.ep; int spurious = 1; - u32 val, tmp; + u32 val_l0, val, tmp; - val = appl_readl(pcie, APPL_INTR_STATUS_L0); - if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { + val_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0); + if (val_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) { val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); @@ -636,7 +636,7 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) spurious = 0; } - if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { + if (val_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); @@ -648,8 +648,8 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) if (spurious) { dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", - val); - appl_writel(pcie, val, APPL_INTR_STATUS_L0); + val_l0); + appl_writel(pcie, val_l0, APPL_INTR_STATUS_L0); } return IRQ_HANDLED;