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Sun, 6 Jun 2021 08:22:30 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 6 Jun 2021 08:22:29 +0000 Received: from buildserver-hdc-comms.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 6 Jun 2021 08:22:26 +0000 From: Om Prakash Singh To: , , , , , , CC: , , , , , Om Prakash Singh Subject: [PATCH V2 3/5] PCI: tegra: Disable interrupts before entering L2 Date: Sun, 6 Jun 2021 13:52:02 +0530 Message-ID: <20210606082204.14222-4-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210606082204.14222-1-omp@nvidia.com> References: <20210606082204.14222-1-omp@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bfe846f1-e990-4bea-89ca-08d928c43a74 X-MS-TrafficTypeDiagnostic: MN2PR12MB4439: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:849; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2021 08:22:30.7913 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfe846f1-e990-4bea-89ca-08d928c43a74 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4439 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In suspend_noirq() call if link doesn't goto L2, PERST# is asserted to bring link to detect state. However, this is causing surprise link down AER error. Since Kernel is executing noirq suspend calls, AER interrupt is not processed. PME and AER are shared interrupts and PCIe subsystem driver enables wake capability of PME irq during suspend. So this AER will cause suspend failure due to pending AER interrupt. After PCIe link is in L2, interrupts are not expected since PCIe controller will be in reset state. Disable PCIe interrupts before going to L2 state to avoid pending AER interrupt. Signed-off-by: Om Prakash Singh Acked-by: Vidya Sagar --- Changes in V2: - Rephrase the commit message as per comment from Krzysztof Wilczyński drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 66e00b276cd3..64ec0da31b5b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1593,6 +1593,16 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) return; } + /* + * PCIe controller exits from L2 only if reset is applied, so + * controller doesn't handle interrupts. But in cases where + * L2 entry fails, PERST# is asserted which can trigger surprise + * link down AER. However this function call happens in + * suspend_noirq(), so AER interrupt will not be processed. + * Disable all interrupts to avoid such a scenario. + */ + appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0); + if (tegra_pcie_try_link_l2(pcie)) { dev_info(pcie->dev, "Link didn't transition to L2 state\n"); /*