From patchwork Thu Jun 24 22:26:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12343289 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFF37C49EA7 for ; Thu, 24 Jun 2021 22:27:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CEC0F61361 for ; Thu, 24 Jun 2021 22:27:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232870AbhFXW3d (ORCPT ); Thu, 24 Jun 2021 18:29:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:38132 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232873AbhFXW3b (ORCPT ); Thu, 24 Jun 2021 18:29:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 06FA561375; Thu, 24 Jun 2021 22:27:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624573632; bh=jYt5kfZFIc6erlp5/8lvnkSBPgbQ6DNhQvJQ28jGNJ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kd7vizbDFBauhateivIkhyAS7AStROoZqtwp9gkAiGOj8di81tHkRcunYn1wtYuzh XqDNQnlAa6wyt8vcP0gpp4vSvvPoiorZ3mYKq1glVKQTciW2RU4mkeEVekVbFaOHIB VjdFIvkfmN+SdxOIvmvQuRrVx9Ykkyd83yivSCXPPcFix1t9pNrj3RteUBRnffiri7 95Te6fuY3YMGppRmo5jReHWcsh2ckNXzdzlZ4k5XDnf/BTS3iA+RPHMXX++5NHalIs ivePIe8pYmt4NkbgX4Og9rw+vsbuYJuIdhoMCwuJbjQ80f+wYwrP9Q5oUXx9ejJtlj dAfODsxjJ6Rhg== Received: by pali.im (Postfix) id B87C88A3; Fri, 25 Jun 2021 00:27:11 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring , Gregory Clement Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , "Remi Pommarel" , Xogium , "Tomasz Maciej Nowak" , Nadav Haklai , Kostya Porotchkin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH 5/5] PCI: aardvark: Implement workaround for PCIe Completion Timeout Date: Fri, 25 Jun 2021 00:26:21 +0200 Message-Id: <20210624222621.4776-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210624222621.4776-1-pali@kernel.org> References: <20210624222621.4776-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251), that PCIe IP does not support a strong-ordered model for inbound posted vs. outbound completion. As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control register must be set. It disables the ordering check in the core between Completions and Posted requests received from the link. It was reported that enabling this workaround fixes instability issues and "Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm QCA6335 chip under significant load which were caused by interrupt status stuck in the outbound CMPLT queue traced back to this erratum. This workaround fixes also kernel panic triggered after some minutes of usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip: Internal error: synchronous external abort: 96000210 [#1] SMP Kernel panic - not syncing: Fatal exception in interrupt Signed-off-by: Thomas Petazzoni Signed-off-by: Pali Rohár Cc: stable@vger.kernel.org --- Patch was originally written by Thomas and is already for a long time part of Marvell SDK. I have just re-written/re-applied it on top of mainline kernel and also wrote a new updated commit message. Please note that this patch is questionable as Bjorn has some objections and nobody, including Marvell, was not able to explain erratum nor what is workaround exactly doing. Documentation about this topic is basically missing. We just know that it fixes real kernel crashes when using WiFi cards. --- drivers/pci/controller/pci-aardvark.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 9ff68abd8d1e..231f4469d87e 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -167,6 +167,8 @@ #define LTSSM_L0 0x10 #define RC_BAR_CONFIG 0x300 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) +#define DEBUG_MUX_CTRL_REG (LMI_BASE_ADDR + 0x208) +#define DIS_ORD_CHK BIT(30) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -450,6 +452,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) PCIE_CORE_CTRL2_TD_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); + /* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */ + reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG); + reg |= DIS_ORD_CHK; + advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG); + /* Set lane X1 */ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg &= ~LANE_CNT_MSK;