| Message ID | 20210625093030.3698570-3-chenhuacai@loongson.cn (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | PCI: Loongson-related pci quirks | expand |
On Fri, Jun 25, 2021 at 05:30:28PM +0800, Huacai Chen wrote: > Loongson PCH (LS7A chipset) will be used by both MIPS-based and > LoongArch-based Loongson processors. MIPS-based Loongson uses FDT > but LoongArch-base Loongson uses ACPI, but the driver in drivers/ > pci/controller/pci-loongson.c is FDT-only. So move the quirks to > quirks.c where can be shared by all architectures. > > LoongArch is a new RISC ISA, mainline support will come soon, and > documentations are here (in translation): > > https://github.com/loongson/LoongArch-Documentation > > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> > --- > drivers/pci/controller/pci-loongson.c | 69 --------------------------- > drivers/pci/quirks.c | 69 +++++++++++++++++++++++++++ > 2 files changed, 69 insertions(+), 69 deletions(-) > > diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c > index 48169b1e3817..88066e9db69e 100644 > --- a/drivers/pci/controller/pci-loongson.c > +++ b/drivers/pci/controller/pci-loongson.c > @@ -12,15 +12,6 @@ > > #include "../pci.h" > > -/* Device IDs */ > -#define DEV_PCIE_PORT_0 0x7a09 > -#define DEV_PCIE_PORT_1 0x7a19 > -#define DEV_PCIE_PORT_2 0x7a29 > - > -#define DEV_LS2K_APB 0x7a02 > -#define DEV_LS7A_CONF 0x7a10 > -#define DEV_LS7A_LPC 0x7a0c > - > #define FLAG_CFG0 BIT(0) > #define FLAG_CFG1 BIT(1) > #define FLAG_DEV_FIX BIT(2) > @@ -32,66 +23,6 @@ struct loongson_pci { > u32 flags; > }; > > -/* Fixup wrong class code in PCIe bridges */ > -static void bridge_class_quirk(struct pci_dev *dev) > -{ > - dev->class = PCI_CLASS_BRIDGE_PCI << 8; > -} > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > - DEV_PCIE_PORT_0, bridge_class_quirk); > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > - DEV_PCIE_PORT_1, bridge_class_quirk); > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > - DEV_PCIE_PORT_2, bridge_class_quirk); > - > -static void system_bus_quirk(struct pci_dev *pdev) > -{ > - /* > - * The address space consumed by these devices is outside the > - * resources of the host bridge. > - */ > - pdev->mmio_always_on = 1; > - pdev->non_compliant_bars = 1; > -} > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > - DEV_LS2K_APB, system_bus_quirk); > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > - DEV_LS7A_CONF, system_bus_quirk); > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > - DEV_LS7A_LPC, system_bus_quirk); > - > -static void loongson_mrrs_quirk(struct pci_dev *dev) > -{ > - struct pci_bus *bus = dev->bus; > - struct pci_dev *bridge; > - static const struct pci_device_id bridge_devids[] = { > - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) }, > - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) }, > - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) }, > - { 0, }, > - }; > - > - /* look for the matching bridge */ > - while (!pci_is_root_bus(bus)) { > - bridge = bus->self; > - bus = bus->parent; > - /* > - * Some Loongson PCIe ports have a h/w limitation of > - * 256 bytes maximum read request size. They can't handle > - * anything larger than this. So force this limit on > - * any devices attached under these ports. > - */ > - if (pci_match_id(bridge_devids, bridge)) { > - if (pcie_get_readrq(dev) > 256) { > - pci_info(dev, "limiting MRRS to 256\n"); > - pcie_set_readrq(dev, 256); > - } > - break; > - } > - } > -} > -DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk); > - > static void __iomem *cfg1_map(struct loongson_pci *priv, int bus, > unsigned int devfn, int where) > { > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index 22b2bb1109c9..dee4798a49fc 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -205,6 +205,75 @@ static void quirk_mmio_always_on(struct pci_dev *dev) > DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, > PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); > > +/* Loongson-related quirks */ > +#define DEV_PCIE_PORT_0 0x7a09 > +#define DEV_PCIE_PORT_1 0x7a19 > +#define DEV_PCIE_PORT_2 0x7a29 > + > +#define DEV_LS2K_APB 0x7a02 > +#define DEV_LS7A_CONF 0x7a10 > +#define DEV_LS7A_LPC 0x7a0c > + > +/* Fixup wrong class code in PCIe bridges */ > +static void loongson_bridge_class_quirk(struct pci_dev *dev) > +{ > + dev->class = PCI_CLASS_BRIDGE_PCI << 8; > +} > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > + DEV_PCIE_PORT_0, loongson_bridge_class_quirk); > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > + DEV_PCIE_PORT_1, loongson_bridge_class_quirk); > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > + DEV_PCIE_PORT_2, loongson_bridge_class_quirk); > + > +static void loongson_system_bus_quirk(struct pci_dev *pdev) > +{ > + /* > + * The address space consumed by these devices is outside the > + * resources of the host bridge. > + */ > + pdev->mmio_always_on = 1; > + pdev->non_compliant_bars = 1; > +} > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > + DEV_LS2K_APB, loongson_system_bus_quirk); > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > + DEV_LS7A_CONF, loongson_system_bus_quirk); > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > + DEV_LS7A_LPC, loongson_system_bus_quirk); > + > +static void loongson_mrrs_quirk(struct pci_dev *dev) > +{ > + struct pci_bus *bus = dev->bus; > + struct pci_dev *bridge; > + static const struct pci_device_id bridge_devids[] = { > + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) }, > + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) }, > + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) }, > + { 0, }, > + }; > + > + /* look for the matching bridge */ > + while (!pci_is_root_bus(bus)) { > + bridge = bus->self; > + bus = bus->parent; > + /* > + * Some Loongson PCIe ports have a h/w limitation of > + * 256 bytes maximum read request size. They can't handle > + * anything larger than this. So force this limit on > + * any devices attached under these ports. > + */ > + if (pci_match_id(bridge_devids, bridge)) { > + if (pcie_get_readrq(dev) > 256) { > + pci_info(dev, "limiting MRRS to 256\n"); > + pcie_set_readrq(dev, 256); > + } > + break; > + } > + } > +} > +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk); I don't want to run this quirk on *every* PCI device on *every* system in the world when the defect is not even in these devices at all. The defect is apparently in some Loongson hardware, so the quirk should somehow be limited to that. > /* > * The Mellanox Tavor device gives false positive parity errors. Disable > * parity error reporting. > -- > 2.27.0 >
Hi, Bjorn, On Sat, Jun 26, 2021 at 11:39 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Jun 25, 2021 at 05:30:28PM +0800, Huacai Chen wrote: > > Loongson PCH (LS7A chipset) will be used by both MIPS-based and > > LoongArch-based Loongson processors. MIPS-based Loongson uses FDT > > but LoongArch-base Loongson uses ACPI, but the driver in drivers/ > > pci/controller/pci-loongson.c is FDT-only. So move the quirks to > > quirks.c where can be shared by all architectures. > > > > LoongArch is a new RISC ISA, mainline support will come soon, and > > documentations are here (in translation): > > > > https://github.com/loongson/LoongArch-Documentation > > > > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> > > --- > > drivers/pci/controller/pci-loongson.c | 69 --------------------------- > > drivers/pci/quirks.c | 69 +++++++++++++++++++++++++++ > > 2 files changed, 69 insertions(+), 69 deletions(-) > > > > diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c > > index 48169b1e3817..88066e9db69e 100644 > > --- a/drivers/pci/controller/pci-loongson.c > > +++ b/drivers/pci/controller/pci-loongson.c > > @@ -12,15 +12,6 @@ > > > > #include "../pci.h" > > > > -/* Device IDs */ > > -#define DEV_PCIE_PORT_0 0x7a09 > > -#define DEV_PCIE_PORT_1 0x7a19 > > -#define DEV_PCIE_PORT_2 0x7a29 > > - > > -#define DEV_LS2K_APB 0x7a02 > > -#define DEV_LS7A_CONF 0x7a10 > > -#define DEV_LS7A_LPC 0x7a0c > > - > > #define FLAG_CFG0 BIT(0) > > #define FLAG_CFG1 BIT(1) > > #define FLAG_DEV_FIX BIT(2) > > @@ -32,66 +23,6 @@ struct loongson_pci { > > u32 flags; > > }; > > > > -/* Fixup wrong class code in PCIe bridges */ > > -static void bridge_class_quirk(struct pci_dev *dev) > > -{ > > - dev->class = PCI_CLASS_BRIDGE_PCI << 8; > > -} > > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > - DEV_PCIE_PORT_0, bridge_class_quirk); > > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > - DEV_PCIE_PORT_1, bridge_class_quirk); > > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > - DEV_PCIE_PORT_2, bridge_class_quirk); > > - > > -static void system_bus_quirk(struct pci_dev *pdev) > > -{ > > - /* > > - * The address space consumed by these devices is outside the > > - * resources of the host bridge. > > - */ > > - pdev->mmio_always_on = 1; > > - pdev->non_compliant_bars = 1; > > -} > > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > - DEV_LS2K_APB, system_bus_quirk); > > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > - DEV_LS7A_CONF, system_bus_quirk); > > -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > - DEV_LS7A_LPC, system_bus_quirk); > > - > > -static void loongson_mrrs_quirk(struct pci_dev *dev) > > -{ > > - struct pci_bus *bus = dev->bus; > > - struct pci_dev *bridge; > > - static const struct pci_device_id bridge_devids[] = { > > - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) }, > > - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) }, > > - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) }, > > - { 0, }, > > - }; > > - > > - /* look for the matching bridge */ > > - while (!pci_is_root_bus(bus)) { > > - bridge = bus->self; > > - bus = bus->parent; > > - /* > > - * Some Loongson PCIe ports have a h/w limitation of > > - * 256 bytes maximum read request size. They can't handle > > - * anything larger than this. So force this limit on > > - * any devices attached under these ports. > > - */ > > - if (pci_match_id(bridge_devids, bridge)) { > > - if (pcie_get_readrq(dev) > 256) { > > - pci_info(dev, "limiting MRRS to 256\n"); > > - pcie_set_readrq(dev, 256); > > - } > > - break; > > - } > > - } > > -} > > -DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk); > > - > > static void __iomem *cfg1_map(struct loongson_pci *priv, int bus, > > unsigned int devfn, int where) > > { > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > > index 22b2bb1109c9..dee4798a49fc 100644 > > --- a/drivers/pci/quirks.c > > +++ b/drivers/pci/quirks.c > > @@ -205,6 +205,75 @@ static void quirk_mmio_always_on(struct pci_dev *dev) > > DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, > > PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); > > > > +/* Loongson-related quirks */ > > +#define DEV_PCIE_PORT_0 0x7a09 > > +#define DEV_PCIE_PORT_1 0x7a19 > > +#define DEV_PCIE_PORT_2 0x7a29 > > + > > +#define DEV_LS2K_APB 0x7a02 > > +#define DEV_LS7A_CONF 0x7a10 > > +#define DEV_LS7A_LPC 0x7a0c > > + > > +/* Fixup wrong class code in PCIe bridges */ > > +static void loongson_bridge_class_quirk(struct pci_dev *dev) > > +{ > > + dev->class = PCI_CLASS_BRIDGE_PCI << 8; > > +} > > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > + DEV_PCIE_PORT_0, loongson_bridge_class_quirk); > > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > + DEV_PCIE_PORT_1, loongson_bridge_class_quirk); > > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > + DEV_PCIE_PORT_2, loongson_bridge_class_quirk); > > + > > +static void loongson_system_bus_quirk(struct pci_dev *pdev) > > +{ > > + /* > > + * The address space consumed by these devices is outside the > > + * resources of the host bridge. > > + */ > > + pdev->mmio_always_on = 1; > > + pdev->non_compliant_bars = 1; > > +} > > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > + DEV_LS2K_APB, loongson_system_bus_quirk); > > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > + DEV_LS7A_CONF, loongson_system_bus_quirk); > > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > > + DEV_LS7A_LPC, loongson_system_bus_quirk); > > + > > +static void loongson_mrrs_quirk(struct pci_dev *dev) > > +{ > > + struct pci_bus *bus = dev->bus; > > + struct pci_dev *bridge; > > + static const struct pci_device_id bridge_devids[] = { > > + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) }, > > + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) }, > > + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) }, > > + { 0, }, > > + }; > > + > > + /* look for the matching bridge */ > > + while (!pci_is_root_bus(bus)) { > > + bridge = bus->self; > > + bus = bus->parent; > > + /* > > + * Some Loongson PCIe ports have a h/w limitation of > > + * 256 bytes maximum read request size. They can't handle > > + * anything larger than this. So force this limit on > > + * any devices attached under these ports. > > + */ > > + if (pci_match_id(bridge_devids, bridge)) { > > + if (pcie_get_readrq(dev) > 256) { > > + pci_info(dev, "limiting MRRS to 256\n"); > > + pcie_set_readrq(dev, 256); > > + } > > + break; > > + } > > + } > > +} > > +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk); > > I don't want to run this quirk on *every* PCI device on *every* system > in the world when the defect is not even in these devices at all. The > defect is apparently in some Loongson hardware, so the quirk should > somehow be limited to that. I'm very sorry that you have told me this problem twice but I forgot it later, I will improve in the next version. Huacai > > > /* > > * The Mellanox Tavor device gives false positive parity errors. Disable > > * parity error reporting. > > -- > > 2.27.0 > >
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c index 48169b1e3817..88066e9db69e 100644 --- a/drivers/pci/controller/pci-loongson.c +++ b/drivers/pci/controller/pci-loongson.c @@ -12,15 +12,6 @@ #include "../pci.h" -/* Device IDs */ -#define DEV_PCIE_PORT_0 0x7a09 -#define DEV_PCIE_PORT_1 0x7a19 -#define DEV_PCIE_PORT_2 0x7a29 - -#define DEV_LS2K_APB 0x7a02 -#define DEV_LS7A_CONF 0x7a10 -#define DEV_LS7A_LPC 0x7a0c - #define FLAG_CFG0 BIT(0) #define FLAG_CFG1 BIT(1) #define FLAG_DEV_FIX BIT(2) @@ -32,66 +23,6 @@ struct loongson_pci { u32 flags; }; -/* Fixup wrong class code in PCIe bridges */ -static void bridge_class_quirk(struct pci_dev *dev) -{ - dev->class = PCI_CLASS_BRIDGE_PCI << 8; -} -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, - DEV_PCIE_PORT_0, bridge_class_quirk); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, - DEV_PCIE_PORT_1, bridge_class_quirk); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, - DEV_PCIE_PORT_2, bridge_class_quirk); - -static void system_bus_quirk(struct pci_dev *pdev) -{ - /* - * The address space consumed by these devices is outside the - * resources of the host bridge. - */ - pdev->mmio_always_on = 1; - pdev->non_compliant_bars = 1; -} -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, - DEV_LS2K_APB, system_bus_quirk); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, - DEV_LS7A_CONF, system_bus_quirk); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, - DEV_LS7A_LPC, system_bus_quirk); - -static void loongson_mrrs_quirk(struct pci_dev *dev) -{ - struct pci_bus *bus = dev->bus; - struct pci_dev *bridge; - static const struct pci_device_id bridge_devids[] = { - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) }, - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) }, - { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) }, - { 0, }, - }; - - /* look for the matching bridge */ - while (!pci_is_root_bus(bus)) { - bridge = bus->self; - bus = bus->parent; - /* - * Some Loongson PCIe ports have a h/w limitation of - * 256 bytes maximum read request size. They can't handle - * anything larger than this. So force this limit on - * any devices attached under these ports. - */ - if (pci_match_id(bridge_devids, bridge)) { - if (pcie_get_readrq(dev) > 256) { - pci_info(dev, "limiting MRRS to 256\n"); - pcie_set_readrq(dev, 256); - } - break; - } - } -} -DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk); - static void __iomem *cfg1_map(struct loongson_pci *priv, int bus, unsigned int devfn, int where) { diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 22b2bb1109c9..dee4798a49fc 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -205,6 +205,75 @@ static void quirk_mmio_always_on(struct pci_dev *dev) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); +/* Loongson-related quirks */ +#define DEV_PCIE_PORT_0 0x7a09 +#define DEV_PCIE_PORT_1 0x7a19 +#define DEV_PCIE_PORT_2 0x7a29 + +#define DEV_LS2K_APB 0x7a02 +#define DEV_LS7A_CONF 0x7a10 +#define DEV_LS7A_LPC 0x7a0c + +/* Fixup wrong class code in PCIe bridges */ +static void loongson_bridge_class_quirk(struct pci_dev *dev) +{ + dev->class = PCI_CLASS_BRIDGE_PCI << 8; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, + DEV_PCIE_PORT_0, loongson_bridge_class_quirk); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, + DEV_PCIE_PORT_1, loongson_bridge_class_quirk); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, + DEV_PCIE_PORT_2, loongson_bridge_class_quirk); + +static void loongson_system_bus_quirk(struct pci_dev *pdev) +{ + /* + * The address space consumed by these devices is outside the + * resources of the host bridge. + */ + pdev->mmio_always_on = 1; + pdev->non_compliant_bars = 1; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, + DEV_LS2K_APB, loongson_system_bus_quirk); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, + DEV_LS7A_CONF, loongson_system_bus_quirk); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, + DEV_LS7A_LPC, loongson_system_bus_quirk); + +static void loongson_mrrs_quirk(struct pci_dev *dev) +{ + struct pci_bus *bus = dev->bus; + struct pci_dev *bridge; + static const struct pci_device_id bridge_devids[] = { + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) }, + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) }, + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) }, + { 0, }, + }; + + /* look for the matching bridge */ + while (!pci_is_root_bus(bus)) { + bridge = bus->self; + bus = bus->parent; + /* + * Some Loongson PCIe ports have a h/w limitation of + * 256 bytes maximum read request size. They can't handle + * anything larger than this. So force this limit on + * any devices attached under these ports. + */ + if (pci_match_id(bridge_devids, bridge)) { + if (pcie_get_readrq(dev) > 256) { + pci_info(dev, "limiting MRRS to 256\n"); + pcie_set_readrq(dev, 256); + } + break; + } + } +} +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk); + /* * The Mellanox Tavor device gives false positive parity errors. Disable * parity error reporting.
Loongson PCH (LS7A chipset) will be used by both MIPS-based and LoongArch-based Loongson processors. MIPS-based Loongson uses FDT but LoongArch-base Loongson uses ACPI, but the driver in drivers/ pci/controller/pci-loongson.c is FDT-only. So move the quirks to quirks.c where can be shared by all architectures. LoongArch is a new RISC ISA, mainline support will come soon, and documentations are here (in translation): https://github.com/loongson/LoongArch-Documentation Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> --- drivers/pci/controller/pci-loongson.c | 69 --------------------------- drivers/pci/quirks.c | 69 +++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 69 deletions(-)