From patchwork Wed Jun 30 02:49:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 12351081 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C84D3C11F6A for ; Wed, 30 Jun 2021 02:50:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE18C61D90 for ; Wed, 30 Jun 2021 02:50:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232892AbhF3Cw0 (ORCPT ); Tue, 29 Jun 2021 22:52:26 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:43213 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232663AbhF3Cw0 (ORCPT ); Tue, 29 Jun 2021 22:52:26 -0400 X-UUID: cd65ef81bacb43dba738c7c7e2399155-20210630 X-UUID: cd65ef81bacb43dba738c7c7e2399155-20210630 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1560391563; Wed, 30 Jun 2021 10:49:55 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Jun 2021 10:49:53 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Jun 2021 10:49:52 +0800 From: Jianjun Wang To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee , Matthias Brugger CC: , , , , , Jianjun Wang , , , , , , , Krzysztof Wilczyski , Subject: [PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request Date: Wed, 30 Jun 2021 10:49:33 +0800 Message-ID: <20210630024934.18903-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210630024934.18903-1-jianjun.wang@mediatek.com> References: <20210630024934.18903-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add property to disable dvfsrc voltage request, if this property is presented, we assume that the requested voltage is always higher enough to keep the PCIe controller active. Signed-off-by: Jianjun Wang Reviewed-by: Qizhong Cheng Tested-by: Qizhong Cheng --- .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index e7b1f9892da4..3e26c032cea9 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -96,6 +96,12 @@ properties: phys: maxItems: 1 + disable-dvfsrc-vlt-req: + description: Disable dvfsrc voltage request, if this property is presented, + we assume that the requested voltage is always higher enough to keep + the PCIe controller active. + type: boolean + '#interrupt-cells': const: 1 @@ -166,6 +172,8 @@ examples: <&infracfg_rst 3>; reset-names = "phy", "mac"; + disable-dvfsrc-vlt-req; + #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc 0>,