From patchwork Wed Jul 21 19:11:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12391971 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01425C636C9 for ; Wed, 21 Jul 2021 19:28:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD2D261264 for ; Wed, 21 Jul 2021 19:28:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240205AbhGUSrr (ORCPT ); Wed, 21 Jul 2021 14:47:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240182AbhGUSrq (ORCPT ); Wed, 21 Jul 2021 14:47:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D825FC061575; Wed, 21 Jul 2021 12:28:22 -0700 (PDT) Message-Id: <20210721192650.408910288@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1626895701; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=KWtC2UPjPY3Lp8DJcp7b3mXMDtwP0YVFUEtqHXYFvGM=; b=ij+tOA1+22K/HklGs9TlrUVUZV7/dMj5ggQdcdg4/57Joy0kopGpeFPXbAnmFRxrgbjXjy gBtiVkrAcNtp9USFAuKm2Vp5Qf6fK/qjK6DftI2L3SfNlP9V9z6A0npWUrV28lAWcZpTLF Vjz5WNoSi8hZ9m7yRF9+IYP7Ei+w2f8nGPAb6IWIqLBwM2Mxg30OSC0EEZF0W0qH4GycTv iQsHx4Bl7h5549h4be8xIWzLq4Vzg6Z+8CzKwPf+iUtItG9IBq382EYnfNzoWloMN5yHYs mD4nJDXUewubAc463bk0IUhUuGCFEHpqr5VqQCjcBePNkymgS1LMG4epcOskMQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1626895701; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=KWtC2UPjPY3Lp8DJcp7b3mXMDtwP0YVFUEtqHXYFvGM=; b=8asa2EORheXG28I5hV5q2mJLgfLpZhlup17vHg1Xv3nEz8yqaK8FPoYNetz2p2jHfMyXdh GhiEdrx0B3LPWYCw== Date: Wed, 21 Jul 2021 21:11:29 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , Kevin Tian , Bjorn Helgaas , linux-pci@vger.kernel.org, "David S. Miller" , Marc Zyngier , Ingo Molnar , x86@kernel.org Subject: [patch 3/8] PCI/MSI: Enforce that MSI-X table entry is masked for update References: <20210721191126.274946280@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The specification states: For MSI-X, a function is permitted to cache Address and Data values from unmasked MSI-X Table entries. However, anytime software unmasks a currently masked MSI-X Table entry either by clearing its Mask bit or by clearing the Function Mask bit, the function must update any Address or Data values that it cached from that entry. If software changes the Address or Data value of an entry while the entry is unmasked, the result is undefined. The Linux kernel's MSI-X support never enforced that the entry is masked before the entry is modified hence the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Enforce the entry to be masked across the update. There is no point in enforcing this to be handled at all possible call sites as this is just pointless code duplication and the common update function is the obvious place to enforce this. Reported-by: Kevin Tian Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Signed-off-by: Thomas Gleixner Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org --- drivers/pci/msi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -289,13 +289,28 @@ void __pci_write_msi_msg(struct msi_desc /* Don't touch the hardware now */ } else if (entry->msi_attrib.is_msix) { void __iomem *base = pci_msix_desc_addr(entry); + bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT); if (!base) goto skip; + /* + * The specification mandates that the entry is masked + * when the message is modified: + * + * "If software changes the Address or Data value of an + * entry while the entry is unmasked, the result is + * undefined." + */ + if (unmasked) + __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT); + writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->data, base + PCI_MSIX_ENTRY_DATA); + + if (unmasked) + __pci_msix_desc_mask_irq(entry, 0); } else { int pos = dev->msi_cap; u16 msgctl;