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[104.194.74.249]) by smtp.gmail.com with ESMTPSA id r29sm1414076pfq.102.2021.07.26.19.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jul 2021 19:30:13 -0700 (PDT) From: Artem Lapkin X-Google-Original-From: Artem Lapkin To: narmstrong@baylibre.com Cc: yue.wang@Amlogic.com, khilman@baylibre.com, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, jbrunet@baylibre.com, christianshewitt@gmail.com, martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, art@khadas.com, nick@khadas.com, gouwa@khadas.com Subject: [PATCH v2] PCI: DWC: meson: add 256 bytes MRRS quirk Date: Tue, 27 Jul 2021 10:30:00 +0800 Message-Id: <20210727023000.1030525-1-art@khadas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org 256 bytes maximum read request size. They can't handle anything larger than this. So force this limit on any devices attached under these ports. Come-from: https://lkml.org/lkml/2021/6/18/160 Come-from: https://lkml.org/lkml/2021/6/19/19 It only affects PCIe in P2P, in non-P2P is will certainly affect transfers on the internal SoC/Processor/Chip internal bus/fabric. These quirks are currently implemented in the controller driver and only applies when the controller has been probed and to each endpoint detected on this particular controller. Continue having separate quirks for each controller if the core isn't the right place to handle MPS/MRRS. >> Neil Signed-off-by: Artem Lapkin --- drivers/pci/controller/dwc/pci-meson.c | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index 686ded034..1498950de 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -466,6 +466,37 @@ static int meson_pcie_probe(struct platform_device *pdev) return ret; } +static void meson_mrrs_limit_quirk(struct pci_dev *dev) +{ + struct pci_bus *bus = dev->bus; + int mrrs, mrrs_limit = 256; + static const struct pci_device_id bridge_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3) }, + { 0, }, + }; + + /* look for the matching bridge */ + while (!pci_is_root_bus(bus)) { + /* + * 256 bytes maximum read request size. They can't handle + * anything larger than this. So force this limit on + * any devices attached under these ports. + */ + if (!pci_match_id(bridge_devids, bus->self)) { + bus = bus->parent; + continue; + } + + mrrs = pcie_get_readrq(dev); + if (mrrs > mrrs_limit) { + pci_info(dev, "limiting MRRS %d to %d\n", mrrs, mrrs_limit); + pcie_set_readrq(dev, mrrs_limit); + } + break; + } +} +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, meson_mrrs_limit_quirk); + static const struct of_device_id meson_pcie_of_match[] = { { .compatible = "amlogic,axg-pcie",