From patchwork Thu Jul 29 21:51:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409969 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AAA5C4320A for ; Thu, 29 Jul 2021 22:34:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 17D1F61055 for ; Thu, 29 Jul 2021 22:34:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233341AbhG2Weu (ORCPT ); Thu, 29 Jul 2021 18:34:50 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49076 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233247AbhG2Wet (ORCPT ); Thu, 29 Jul 2021 18:34:49 -0400 Message-ID: <20210729222542.515188147@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=Jk5SWiz4zixJPTPHbu/FUC3Ud8rM85M9ZKpgM4tFAHQ=; b=oynYxQGHwe7YFlYp72SfHF9qpOFMr9z+XbXN9t6LNltnPOPzI10qhsi4aVXgG3w2wBgJSa PAQorvzKkGtLMV21ukE5KZNKyGjdLOxoAVAr1RDn6aBiwPpHiQ2Jmsfp2jpvMYveco8zfK bie4iUIvUCXRaWF8/lkmMKSV7EmjoKO1fZpKCoS/hW+CUvupxFvxSWB7oDbAI9GH8Zc0oW 7qTX/uh01xpdCTnXnWSjpir/8Ko16jxp2Dz3ciiEl++oKQVKUtaH+aJqZZEMQF9SAWB3AM qtn9clB2U+S8mOMGxVLIsIn2CqjP5o+R1l4m0UfWiYprqZX1ZyxBW+xd5D2GTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=Jk5SWiz4zixJPTPHbu/FUC3Ud8rM85M9ZKpgM4tFAHQ=; b=PilEaf04chh3LEQY+bW6AWc6ThmBtbyWE9EHjoRe2Q3OqXNvl9VY0p/8SPsLRv1HoBpmuL zCfUVmjkMOY/WsBw== Date: Thu, 29 Jul 2021 23:51:43 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 04/19] PCI/MSI: Enforce MSI[X] entry updates to be visible References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner Nothing enforces the posted writes to be visible when the function returns. Flush them even if the flush might be redundant when the entry is masked already as the unmask will flush as well. This is either setup or a rare affinity change event so the extra flush is not the end of the world. While this is more a theoretical issue especially the logic in the X86 specific msi_set_affinity() function relies on the assumption that the update has reached the hardware when the function returns. Again, as this never has been enforced the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas --- drivers/pci/msi.c | 5 +++++ 1 file changed, 5 insertions(+) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -311,6 +311,9 @@ void __pci_write_msi_msg(struct msi_desc if (unmasked) __pci_msix_desc_mask_irq(entry, 0); + + /* Ensure that the writes are visible in the device */ + readl(base + PCI_MSIX_ENTRY_DATA); } else { int pos = dev->msi_cap; u16 msgctl; @@ -331,6 +334,8 @@ void __pci_write_msi_msg(struct msi_desc pci_write_config_word(dev, pos + PCI_MSI_DATA_32, msg->data); } + /* Ensure that the writes are visible in the device */ + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); } skip: