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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id y64sm10344297wmc.38.2021.09.24.14.11.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Sep 2021 14:11:47 -0700 (PDT) From: Sergio Paracuellos To: tsbogend@alpha.franken.de Cc: robh@kernel.org, arnd@arndb.de, catalin.marinas@arm.com, Liviu.Dudau@arm.com, bhelgaas@google.com, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, linux-mips@vger.kernel.org, linux-pci@vger.kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] MIPS: implement architecture dependent 'pci_remap_iospace()' Date: Fri, 24 Sep 2021 23:11:38 +0200 Message-Id: <20210924211139.3477-6-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210924211139.3477-1-sergio.paracuellos@gmail.com> References: <20210924211139.3477-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org To make PCI IO work we need to properly virtually map IO cpu physical address and set this virtual address as the address of the first PCI IO port which is set using function 'set_io_port_base()'. Signed-off-by: Sergio Paracuellos Acked-by: Arnd Bergmann --- arch/mips/include/asm/pci.h | 2 ++ arch/mips/pci/pci-generic.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 9ffc8192adae..35270984a5f0 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -20,6 +20,8 @@ #include #include +#define pci_remap_iospace pci_remap_iospace + #ifdef CONFIG_PCI_DRIVERS_LEGACY /* diff --git a/arch/mips/pci/pci-generic.c b/arch/mips/pci/pci-generic.c index 95b00017886c..877ec9d6a614 100644 --- a/arch/mips/pci/pci-generic.c +++ b/arch/mips/pci/pci-generic.c @@ -46,3 +46,12 @@ void pcibios_fixup_bus(struct pci_bus *bus) { pci_read_bridge_bases(bus); } + +int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) +{ + size_t size = (res->end - res->start) + 1; + unsigned long vaddr = (unsigned long)ioremap(phys_addr, size); + + set_io_port_base(vaddr); + return 0; +}