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Fri, 11 Feb 2022 19:35:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT024.mail.protection.outlook.com (10.13.172.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4975.11 via Frontend Transport; Fri, 11 Feb 2022 19:35:10 +0000 Received: from localhost.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Fri, 11 Feb 2022 13:35:09 -0600 From: Mario Limonciello To: Bjorn Helgaas , Mika Westerberg , "open list:PCI SUBSYSTEM" , "open list:THUNDERBOLT DRIVER" , "open list:RADEON and AMDGPU DRM DRIVERS" , "open list:DRM DRIVERS" , "open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS" CC: Andreas Noever , Michael Jamet , Yehezkel Bernat , "Lukas Wunner" , , Hans de Goede , Mario Limonciello Subject: [PATCH v3 07/12] PCI: Set ports for discrete USB4 controllers appropriately Date: Fri, 11 Feb 2022 13:32:45 -0600 Message-ID: <20220211193250.1904843-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220211193250.1904843-1-mario.limonciello@amd.com> References: <20220211193250.1904843-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 434e9cb5-fad7-4bc9-c74c-08d9ed959e19 X-MS-TrafficTypeDiagnostic: CY4PR1201MB2548:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2022 19:35:10.6941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 434e9cb5-fad7-4bc9-c74c-08d9ed959e19 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB2548 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Discrete USB4 controllers won't have ACPI nodes specifying which PCIe or XHCI port they are linked with. In order to set the removable attribute appropriately, use the USB4 DVSEC extended capabability set on these root ports to determine if they are located on a discrete USB4 controller. Suggested-by: Mika Westerberg Link: https://usb.org/sites/default/files/USB4%20Specification%2020211116.zip Signed-off-by: Mario Limonciello --- drivers/pci/probe.c | 33 +++++++++++++++++++++++++++++++++ include/linux/pci_ids.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 67ca33188cba..1ed3e24db11e 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -25,6 +25,8 @@ #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ #define CARDBUS_RESERVE_BUSNR 3 +#define PCI_DVSEC_ID_USB4 0x23 + static struct resource busn_resource = { .name = "PCI busn", .start = 0, @@ -1590,6 +1592,36 @@ static void set_pcie_untrusted(struct pci_dev *dev) dev->untrusted = true; } +static bool pci_is_discrete_usb4(struct pci_dev *dev) +{ + int dvsec_val = 0, pos; + u32 hdr; + + /* USB4 spec says vendors can use either */ + pos = pci_find_dvsec_capability(dev, + PCI_VENDOR_ID_INTEL, + PCI_DVSEC_ID_USB4); + if (pos) { + dvsec_val = 0x06; + } else { + pos = pci_find_dvsec_capability(dev, + PCI_VENDOR_ID_USB_IF, + PCI_DVSEC_ID_USB4); + if (pos) + dvsec_val = 0x01; + } + if (!dvsec_val) + return false; + + pci_read_config_dword(dev, pos + PCI_DVSEC_HEADER2, &hdr); + if ((hdr & GENMASK(15, 0)) != dvsec_val) + return false; + /* this port is used for either NHI/PCIe tunnel/USB tunnel */ + if (hdr & GENMASK(18, 16)) + return true; + return false; +} + static void pci_set_removable(struct pci_dev *dev) { struct pci_dev *parent = pci_upstream_bridge(dev); @@ -1612,6 +1644,7 @@ static void pci_set_removable(struct pci_dev *dev) if (vsec || dev->class == PCI_CLASS_SERIAL_USB_USB4 || pci_acpi_is_usb4(dev) || + pci_is_discrete_usb4(dev) || (parent && (parent->external_facing || dev_is_removable(&parent->dev)))) dev_set_removable(&dev->dev, DEVICE_REMOVABLE); diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 61b161d914f0..271326e058b9 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -3097,4 +3097,6 @@ #define PCI_VENDOR_ID_NCUBE 0x10ff +#define PCI_VENDOR_ID_USB_IF 0x1EC0 + #endif /* _LINUX_PCI_IDS_H */