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Tue, 15 Feb 2022 04:46:15 -0800 Envelope-to: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, bhelgaas@google.com Received: from [10.140.9.2] (port=50434 helo=xhdbharatku40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nJxDi-000EtN-Oe; Tue, 15 Feb 2022 04:46:15 -0800 From: Bharat Kumar Gogada To: , CC: , , , Bharat Kumar Gogada Subject: [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port Date: Tue, 15 Feb 2022 18:16:05 +0530 Message-ID: <20220215124606.28627-2-bharat.kumar.gogada@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220215124606.28627-1-bharat.kumar.gogada@xilinx.com> References: <20220215124606.28627-1-bharat.kumar.gogada@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 36193b96-7ccb-4c9d-694c-08d9f08127ea X-MS-TrafficTypeDiagnostic: MN2PR02MB5821:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2399; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2022 12:46:15.9350 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36193b96-7ccb-4c9d-694c-08d9f08127ea X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT018.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB5821 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Add support for YAML schemas documentation for Versal CPM5 Root Port driver. Signed-off-by: Bharat Kumar Gogada --- .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 32f4641085bc..97c7229d7f91 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -14,17 +14,21 @@ allOf: properties: compatible: - const: xlnx,versal-cpm-host-1.00 + contains: + enum: + - xlnx,versal-cpm-host-1.00 + - xlnx,versal-cpm5-host-1.00 reg: - items: - - description: Configuration space region and bridge registers. - - description: CPM system level control and status registers. + description: | + Should contain cpm_slcr, cfg registers location and length. + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. + minItems: 2 + maxItems: 3 reg-names: - items: - - const: cfg - - const: cpm_slcr + minItems: 2 + maxItems: 3 interrupts: maxItems: 1 @@ -95,4 +99,33 @@ examples: interrupt-controller; }; }; + + cpm5_pcie: pcie@fcdd0000 { + compatible = "xlnx,versal-cpm5-host-1.00"; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = <0 72 4>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_1 0>, + <0 0 0 2 &pcie_intc_1 1>, + <0 0 0 3 &pcie_intc_1 2>, + <0 0 0 4 &pcie_intc_1 3>; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x00 0xfcdd0000 0x00 0x1000>, + <0x06 0x00000000 0x00 0x1000000>, + <0x00 0xfce20000 0x00 0x1000000>; + reg-names = "cpm_slcr", "cfg", "cpm_csr"; + + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; };