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Mon, 7 Mar 2022 16:24:58 +0000 From: Frank Li To: gustavo.pimentel@synopsys.com, hongxing.zhu@nxp.com, l.stach@pengutronix.de, linux-imx@nxp.com, linux-pci@vger.kernel.org, lznuaa@gmail.com Cc: vkoul@kernel.org, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com, shawnguo@kernel.org, manivannan.sadhasivam@linaro.org Subject: [PATCH v3 3/6] dmaengine: dw-edma: Fix programming the source & dest addresses for ep Date: Mon, 7 Mar 2022 10:24:27 -0600 Message-Id: <20220307162430.15261-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.24.0.rc1 In-Reply-To: <20220307162430.15261-1-Frank.Li@nxp.com> References: <20220307162430.15261-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0146.namprd13.prod.outlook.com (2603:10b6:a03:2c6::31) To PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 775652ea-959a-4750-a484-08da00570560 X-MS-TrafficTypeDiagnostic: AM0PR04MB4530:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Since the Root complex and Endpoint uses the opposite channels for read/write, fix the issue by finding out the read operation first and program the eDMA accordingly. Cc: stable@vger.kernel.org Fixes: bd96f1b2f43a ("dmaengine: dw-edma: support local dma device transfer semantics") Fixes: e63d79d1ffcd ("dmaengine: Add Synopsys eDMA IP core driver") Signed-off-by: Manivannan Sadhasivam --- Change from V1-v3 - Direct pick up from Manivannan drivers/dma/dw-edma/dw-edma-core.c | 32 +++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 0cb66434f9e14..3636c48f5df15 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -334,6 +334,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) struct dw_edma_chunk *chunk; struct dw_edma_burst *burst; struct dw_edma_desc *desc; + bool read = false; u32 cnt = 0; int i; @@ -424,7 +425,36 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) chunk->ll_region.sz += burst->sz; desc->alloc_sz += burst->sz; - if (chan->dir == EDMA_DIR_WRITE) { + /**************************************************************** + * + * Root Complex Endpoint + * +-----------------------+ +----------------------+ + * | | TX CH | | + * | | | | + * | DEV_TO_MEM <-------------+ MEM_TO_DEV | + * | | | | + * | | | | + * | MEM_TO_DEV +-------------> DEV_TO_MEM | + * | | | | + * | | RX CH | | + * +-----------------------+ +----------------------+ + * + * If eDMA is controlled by the Root complex, TX channel + * (EDMA_DIR_WRITE) is used for memory read (DEV_TO_MEM) and RX + * channel (EDMA_DIR_READ) is used for memory write (MEM_TO_DEV). + * + * If eDMA is controlled by the endpoint, RX channel + * (EDMA_DIR_READ) is used for memory read (DEV_TO_MEM) and TX + * channel (EDMA_DIR_WRITE) is used for memory write (MEM_TO_DEV). + * + ****************************************************************/ + + if ((dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_READ) || + (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE)) + read = true; + + /* Program the source and destination addresses for DMA read/write */ + if (read) { burst->sar = src_addr; if (xfer->type == EDMA_XFER_CYCLIC) { burst->dar = xfer->xfer.cyclic.paddr;