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Thu, 10 Mar 2022 19:25:44 +0000 From: Frank Li To: gustavo.pimentel@synopsys.com, hongxing.zhu@nxp.com, l.stach@pengutronix.de, linux-imx@nxp.com, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, fancer.lancer@gmail.com, lznuaa@gmail.com Cc: vkoul@kernel.org, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com, shawnguo@kernel.org, manivannan.sadhasivam@linaro.org Subject: [PATCH v5 7/9] dmaengine: dw-edma: Add support for chip specific flags Date: Thu, 10 Mar 2022 13:24:55 -0600 Message-Id: <20220310192457.3090-8-Frank.Li@nxp.com> X-Mailer: git-send-email 2.24.0.rc1 In-Reply-To: <20220310192457.3090-1-Frank.Li@nxp.com> References: <20220310192457.3090-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR05CA0051.namprd05.prod.outlook.com (2603:10b6:a03:33f::26) To PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ab0062ed-a6c1-4b62-959e-08da02cbc552 X-MS-TrafficTypeDiagnostic: DB7PR04MB4858:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TY1zNgNN8ci6CfXRg3kkxhbRjIPpDV3kfwfW8MIwLIlKM3wK9wPcOe0dP12nxxAoo76y5Xh5DEwmUcG+RPpBzqt2QwaUlNA8Suy3uJ4vXQwYGLiNwpv/olGuzjUdh5zGJFASAXTtLxPlV1iW/KK4j0FeU5d/w7Ovdghiy1slQNkVRNNg90F9OZFdBhJYr0y75ihBEmXXodxt1hXabUHiAGrnI/PCLCsH8mX2/9IoUY4kB4CrJtCmsGklG+6g0JPL7SfJoEk6LXWYQRl06aIkHsYjOHOtI6xy4pwnFtFnlmSQZHv65H4WeWpd304saGhqOdSPuTtGmxSOTu0EhMS7KwVqR09pTcYK/NYWpBcO9S3qapqfUVOkDW/IDqWSkNp75iyGP43XY7FvwWGhoiw60byKD85Hsmu106CU3w9/wjh5lno13YbKLEcWj9s+FP1kQHzSFoNOAJEG8+j91fPjpQN9hgC0D4VfTW1IlDpnI4bvi/Woq9HHxpeUw0thaJT7jlg+c1ogIJomqnwKtirUC0BVbOsAA7K0whNaxTVaHgv2nd1xCgAaszHHBOxQo6H0ph7fDnsJu2jHR9X9DCpEIEjvrCuQbDNV4qFjLY/VJ883fzuy7INXR8fTxSs5hmyiJvHmehg04AWLo222AmjKjTNET5njSROZsI0QqFkqGkwod3fERIlvMomttQgys5h3LbSsUfhynGuQIpxvtPKvb5cBWgR4DVVAXdmTFV6xm8mKm2ZpyOlk21HgADdgEWNnbselxIJvpE7hqkBuV4hjkW1e7b1DKzMAreMBHN8DFGOpBOZ0swO0FbVWcHIrpfUjRXCTLREdZFqkGfhtR6HeHDjEpY6xIIbmR4A3khL3N5JfKO3HQhQBqUkwMaH3uznaoC1ixXCop6v1VT8besBnFC/sJiLYP4WY+IZc6VDNc1vXmAHUdK+/5YdB5PgOAxbr8MOE9DmEalg2uVoCoem8yLe0DaLbPvuZF/6Og/UkGjRqbg++6RuNY8OBa2vC0AxbVhEwa58qtV2+hZM1nc6vAoNbFiUsUw3rNIZzqA77Pr7nQg3qPNykNWuC3pJYcjYTnpZZDJ+LHZarYStxn4szxOlotlJ/d1mTKcjZj07KasCFwCQi6T2zeogoz+AUIEOrfMPFQ6jRmfeSh2e4xGBsN8njP8Ehbkd6mcnHUI0mZsleTRr0mVwdg7OER6n623I+M2ANG0uyHLYtN0CnmTr9dN/nCAPEgz5UDebmxMaRs6pzTHT8pTADSLttQDkv2ubcBZ57VNjaOCnGvHbNoeW+FK87+7GdY/zY/hBMcJwhrlslldon2bVxPzRIqaIZ7yLiRO1GkixO5xsoOfoOkBmMIrrePPhsCutT9hv8BizksFVp71gn8wcOYMOIJy68XbYPe1kNy5ap9JUggymCcSQQUTFAhyreHY18U2i6F75nm04NHb2nGdhzz+bRsi/j7rOf X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ab0062ed-a6c1-4b62-959e-08da02cbc552 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9186.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 19:25:43.9892 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3ikzgrxycx+L5fSOmI80bsEI/JUzC9AW2VmEDvmMz5zuMp+femHmb6NEjQZwHvY6l3DMEOJkVbsjLbmiVoMwfQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4858 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add a "flags" field to the "struct dw_edma_chip" so that the controller drivers can pass flags that are relevant to the platform. DW_EDMA_CHIP_LOCAL - Used by the controller drivers accessing eDMA locally. Local eDMA access doesn't require generating MSIs to the remote. Signed-off-by: Frank Li --- Change from v4 to v5 - split two two patch - rework commit message Change from v3 to v4 none Change from v2 to v3 - rework commit message - Change to DW_EDMA_CHIP_32BIT_DBI - using DW_EDMA_CHIP_LOCAL control msi - Apply Bjorn's comments, if (!j) { control |= DW_EDMA_V0_LIE; if (!(chan->chip->flags & DW_EDMA_CHIP_LOCAL)) control |= DW_EDMA_V0_RIE; } if ((chan->chip->flags & DW_EDMA_CHIP_REG32BIT) || !IS_ENABLED(CONFIG_64BIT)) { SET_CH_32(...); SET_CH_32(...); } else { SET_CH_64(...); } Change from v1 to v2 - none drivers/dma/dw-edma/dw-edma-v0-core.c | 9 ++++++--- include/linux/dma/edma.h | 5 +++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index 35f2adac93e46..30686bfe1790c 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -301,6 +301,7 @@ u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir) static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) { struct dw_edma_burst *child; + struct dw_edma_chan *chan = chunk->chan; struct dw_edma_v0_lli __iomem *lli; struct dw_edma_v0_llp __iomem *llp; u32 control = 0, i = 0; @@ -314,9 +315,11 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) j = chunk->bursts_alloc; list_for_each_entry(child, &chunk->burst->list, list) { j--; - if (!j) - control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE); - + if (!j) { + control |= DW_EDMA_V0_LIE; + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) + control |= DW_EDMA_V0_RIE; + } /* Channel control */ SET_LL_32(&lli[i].control, control); /* Transfer size */ diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index c2039246fc08c..5816c8bdf9a64 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -33,12 +33,16 @@ enum dw_edma_map_format { EDMA_MF_HDMA_COMPAT = 0x5 }; +/* Probe EDMA engine locally and prevent generate MSI to host side*/ +#define DW_EDMA_CHIP_LOCAL BIT(0) + /** * struct dw_edma_chip - representation of DesignWare eDMA controller hardware * @dev: struct device of the eDMA controller * @id: instance ID * @nr_irqs: total dma irq number * @ops DMA channel to IRQ number mapping + * @flags - DW_EDMA_CHIP_LOCAL * @reg_base DMA register base address * @ll_wr_cnt DMA write link list number * @ll_rd_cnt DMA read link list number @@ -53,6 +57,7 @@ struct dw_edma_chip { int id; int nr_irqs; const struct dw_edma_core_ops *ops; + u32 flags; void __iomem *reg_base;