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Thu, 14 Apr 2022 02:23:10 -0700 Envelope-to: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org Received: from [10.140.9.2] (port=38782 helo=xhdbharatku40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nevgz-0008Tv-L2; Thu, 14 Apr 2022 02:23:10 -0700 From: Bharat Kumar Gogada To: , , CC: , , , , Bharat Kumar Gogada Subject: [PATCH v1 3/3] dt-bindings: PCI: xilinx-cpm: Change reg property order Date: Thu, 14 Apr 2022 14:52:52 +0530 Message-ID: <20220414092252.12174-4-bharat.kumar.gogada@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220414092252.12174-1-bharat.kumar.gogada@xilinx.com> References: <20220414092252.12174-1-bharat.kumar.gogada@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: df315099-f6e2-4af9-0580-08da1df86560 X-MS-TrafficTypeDiagnostic: PH0PR02MB7126:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 09:23:11.5451 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df315099-f6e2-4af9-0580-08da1df86560 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0041.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB7126 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Describe cpm reg property name before cfg reg property to align with node name. Signed-off-by: Bharat Kumar Gogada Acked-by: Michal Simek --- .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 4ebcc838a1f6..a3bc6ed9cf95 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -18,13 +18,13 @@ properties: reg: items: - - description: Configuration space region and bridge registers. - description: CPM system level control and status registers. + - description: Configuration space region and bridge registers. reg-names: items: - - const: cfg - const: cpm_slcr + - const: cfg interrupts: maxItems: 1 @@ -86,9 +86,9 @@ examples: ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &its_gic 0x0 0x10000>; - reg = <0x6 0x00000000 0x0 0x10000000>, - <0x0 0xfca10000 0x0 0x1000>; - reg-names = "cfg", "cpm_slcr"; + reg = <0x0 0xfca10000 0x0 0x1000>, + <0x6 0x00000000 0x0 0x10000000>; + reg-names = "cpm_slcr", "cfg"; pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>;