From patchwork Sun Apr 24 13:20:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12824889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4745AC433F5 for ; Sun, 24 Apr 2022 13:20:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234849AbiDXNXo (ORCPT ); Sun, 24 Apr 2022 09:23:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234120AbiDXNXn (ORCPT ); Sun, 24 Apr 2022 09:23:43 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AC01B1ED for ; Sun, 24 Apr 2022 06:20:41 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id w1so21906418lfa.4 for ; Sun, 24 Apr 2022 06:20:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E5gfhqqfjatXbBteVPXIO9+6L0d8Um+h14mjmTgnTNw=; b=KmKc1es+3UoJmdKSxAGbTsn4OPUMT/GzerW5frFBVkxleD7uGNrzEPtqz5e2fUVAvd Mu1EWvdr1lWo73uyVue3uTBL5rpDlArMS2qhwTreUJ3kAy7IPABjKdDFgCL5EDv7k4K0 uq/N6btGl8KivhjgCQbDrRrVNR8NwXIK7HzQRlvBbOZ3oxEAjLMrX9plUECEZ6GSUf85 NdYnu5yPXditNYVzSPJdtFmZwnLqrfE8J0hB32jjX1XkDH6avjhlf83xP34tUCnaE7Mh kM1JNsoBkVbpt4hzt4XTzyEm2Njn9CUUmuTKKdQQnG/D/XsKiL4xC/+NVWpus5I4qKD4 ZWnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E5gfhqqfjatXbBteVPXIO9+6L0d8Um+h14mjmTgnTNw=; b=LB5DXv682HJhi6yPQ7IS3zXT/Okal12iBS+XEG/wPf9HXpU72dX5ax4bOpv3Y/pJmi BU7YIyzxWQRcs6l1hxYrM/RfDWYpa7l8vSqo2+6wezUUCNALNQeyQG9uSBlBiQB3xwGd yz0idym0x5nWbsEmr2xl4aLe5b3iXVpjiEjTWD9asvWG6HcxGv+ltciGY9e0Yywrllwh DqI7K9u+UU/wYRR513M7V5fgxzPegjuK/8KOmXasARvJWRPbCY0JwM/LrioOQVNyT+EE lYbjGrUAR5FH/VuTe/WSu0re5MajAHDWubDVnGsaRnaJLfBojTb5/UZs4CrKBozZWzT6 k1dA== X-Gm-Message-State: AOAM530KA96++Skk9jZ2q9e3svTFkc4XaM1b10UKF5JL80Bwuo24FEvO kVmNz3WhM/OA5JHLPtx6Xjy0bw== X-Google-Smtp-Source: ABdhPJzYYrD1nL6NkdjAGsrpl0vPkWhQQZZbtyoeaDJUR6kMgND323vz6FclUVR8Uxz+g8eGSEWlxA== X-Received: by 2002:ac2:5084:0:b0:471:ccb3:8c99 with SMTP id f4-20020ac25084000000b00471ccb38c99mr9845736lfm.435.1650806439774; Sun, 24 Apr 2022 06:20:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id l12-20020a056512332c00b0046d0e0e5b44sm1015877lfe.20.2022.04.24.06.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 06:20:39 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 5/8] arm64: dts: qcom: stop using snps,dw-pcie falback Date: Sun, 24 Apr 2022 16:20:31 +0300 Message-Id: <20220424132034.2235768-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> References: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Qualcomm PCIe devices are not really compatible with the snps,dw-pcie. Unlike the generic IP core, they have special requirements regarding enabling clocks, toggling resets, using the PHY, etc. This is not to mention that platform snps-dw-pcie driver expects to find two IRQs declared, while Qualcomm platforms use just one. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f0f81c23c16f..b577b9046938 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1574,7 +1574,7 @@ agnoc@0 { ranges; pcie0: pcie@600000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; status = "disabled"; power-domains = <&gcc PCIE0_GDSC>; bus-range = <0x00 0xff>; @@ -1626,7 +1626,7 @@ pcie0: pcie@600000 { }; pcie1: pcie@608000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; power-domains = <&gcc PCIE1_GDSC>; bus-range = <0x00 0xff>; num-lanes = <1>; @@ -1679,7 +1679,7 @@ pcie1: pcie@608000 { }; pcie2: pcie@610000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; power-domains = <&gcc PCIE2_GDSC>; bus-range = <0x00 0xff>; num-lanes = <1>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3f06f7cd3cf2..2386081463e3 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1280,7 +1280,7 @@ glink-edge { }; pcie: pci@10000000 { - compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + compatible = "qcom,pcie-qcs404"; reg = <0x10000000 0xf1d>, <0x10000f20 0xa8>, <0x07780000 0x2000>, diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b31bf62e8680..85dfa0842003 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2027,7 +2027,7 @@ llcc: system-cache-controller@1100000 { }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -2132,7 +2132,7 @@ pcie0_lane: phy@1c06200 { }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + compatible = "qcom,pcie-sdm845"; reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index af8f22636436..410272a1e19b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1789,7 +1789,7 @@ mmss_noc: interconnect@1740000 { }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -1888,7 +1888,7 @@ pcie0_lane: phy@1c06200 { }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, @@ -1994,7 +1994,7 @@ pcie1_lane: phy@1c0e200 { }; pcie2: pci@1c10000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c10000 0 0x3000>, <0 0x64000000 0 0xf1d>, <0 0x64000f20 0 0xa8>,