From patchwork Tue Apr 26 13:21:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 12827147 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58598C433EF for ; Tue, 26 Apr 2022 13:22:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350897AbiDZNZO (ORCPT ); Tue, 26 Apr 2022 09:25:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350862AbiDZNZK (ORCPT ); Tue, 26 Apr 2022 09:25:10 -0400 Received: from mxout4.routing.net (mxout4.routing.net [IPv6:2a03:2900:1:a::9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ADEA33A26; Tue, 26 Apr 2022 06:21:59 -0700 (PDT) Received: from mxbox1.masterlogin.de (unknown [192.168.10.88]) by mxout4.routing.net (Postfix) with ESMTP id CFDF4101299; Tue, 26 Apr 2022 13:21:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1650979317; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VGWdXOAbKYFsWdQ08Ig6m7ORNvxHvLu8Lks5JJidff8=; b=xVPVZVvS74xKRcCQuThE/vqu2FFK5C2u8JUAvtrHNfv79ipesUm4A62gY5k7RfwhcLjC7a tapzdOkHEpT4hNE8OUGpGOTaTg52fx4GTSCaYKDHw298zTf0KCKuMTGoPeCYBanajnPW7U 70XtulkRSbzFo6d7nt6dLD1fdWyXD1w= Received: from localhost.localdomain (fttx-pool-80.245.77.37.bambit.de [80.245.77.37]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id BD203401C9; Tue, 26 Apr 2022 13:21:56 +0000 (UTC) From: Frank Wunderlich To: linux-rockchip@lists.infradead.org Cc: Frank Wunderlich , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Kishon Vijay Abraham I , Vinod Koul , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [RFC/RFT v2 03/11] dt-bindings: phy: rockchip: add PCIe v3 constants Date: Tue, 26 Apr 2022 15:21:31 +0200 Message-Id: <20220426132139.26761-4-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426132139.26761-1-linux@fw-web.de> References: <20220426132139.26761-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 74afaeeb-5fdb-4ebf-b1d4-688c81efa547 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Frank Wunderlich Add constants that can be used in devicetree and driver for PCIe v3 phy. Signed-off-by: Frank Wunderlich --- v2: - new patch because splitting out this file - rename file from snps to rockchip --- include/dt-bindings/phy/phy-rockchip-pcie3.h | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/phy/phy-rockchip-pcie3.h diff --git a/include/dt-bindings/phy/phy-rockchip-pcie3.h b/include/dt-bindings/phy/phy-rockchip-pcie3.h new file mode 100644 index 000000000000..93e57edd337d --- /dev/null +++ b/include/dt-bindings/phy/phy-rockchip-pcie3.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 +#define _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 + +/* + * pcie30_phy_mode[2:0] + * bit2: aggregation + * bit1: bifurcation for port 1 + * bit0: bifurcation for port 0 + */ +#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ +#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ +#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ +#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ +#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ + +#endif /* _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 */