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Tue, 3 May 2022 00:58:57 +0000 From: Frank Li To: gustavo.pimentel@synopsys.com, hongxing.zhu@nxp.com, l.stach@pengutronix.de, linux-imx@nxp.com, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, fancer.lancer@gmail.com, lznuaa@gmail.com, helgaas@kernel.org Cc: vkoul@kernel.org, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, Sergey.Semin@baikalelectronics.ru Subject: [PATCH v10 9/9] PCI: endpoint: Enable DMA controller tests for endpoints with DMA capabilities Date: Mon, 2 May 2022 19:58:01 -0500 Message-Id: <20220503005801.1714345-10-Frank.Li@nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503005801.1714345-1-Frank.Li@nxp.com> References: <20220503005801.1714345-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0P220CA0024.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:41b::32) To PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 68bdb19c-1a58-4d13-d6ee-08da2ca01a01 X-MS-TrafficTypeDiagnostic: VI1PR04MB4431:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Wd/kf/mS6a66hWbAi+29gCweIGMW4yirsC1Ubu9wqXmNdOeD5i0tj7WoEH/B491olIXEDO4IgvXd1EsJwh5/0+cvAD14TuNkICIttm2Ho3K8CwMfUdScoyOaDYHvis1ImTQsPaVGWUkcUfYMOvKAEHnXbYX8hL055JBfoNLGVTBncnKQkSPDxlQo4SVhOTkcwC6fYbvnAdJABNVZCyryMG+gcX/hwqAO8SgSXECJw6eIdQ4McO6IdmXagalQBTScpKfi3siJENBZWVLZ6ZCUGX5rJKkfqfQh1du7SrimFgOheg7UN+KmBdk4Rs0XDGXkP+UioJpr9fDUW1LbQCz/N3J7N+twdEPB3DmpEpL8jKHOIz0M+sWewvyy2w6Kx0HbX0h9FQKmappQIAgSw2nD7pRfs4vi0kV4DKo7luU7VPl9lvQnGFBPpX2RcGCav/XPBhT63y/I42k3x62Fe6ev+qqW/Y1q5WXLpXvnXGBOH/JnnnxlleFLztkbx6COMq6QJGtm3nhZteubgU1XhwMwNQQs2cqa5bptqLB/fWelilJ9m0tSnG1K3EnWxsG8YUE+5THTBxjoOmeQc+MCAS0k1ZMQMv4Wk6RCL4O4z8FQE+TZU2Wal57kVSZKRttGAYd4rezSyHPR0ca6lEVpDiv5XZmRLgnvWG6Bxo2yU0ckD+Tu54pyMQyQr67rmcoIfa9Q1smQT5iYd/iY/kNaJY6C+jMHfjN+ENa015whiBCxDswAdz7Dfv9EjX7DYrlQMaQD0m+82sK514xE/0BgmvUO6r2vMtCNqxCqiuYFmDNhT9Iy/CN10k7OGGLmUxoOYWcQ+wF1l0eFMgs0UtLoeGbIH/tHtZvYAA8h+MtBgTKXO47LOF4BI9/fBL3lI78fSjgKHYJUVXzRilksvcVdeERPs3JkyB0AH0LYttKLnx9fPfwQY7l5HXF7dy/T5wsSoTRiUpMUXHYNLPLLUtYZUowSCESieZ4FVIfdgg6qlbtJfWlR7xR2hJtOY6N68+l/d+lmu/n+RIjzoxHlcqs85A5ZH+RHRGysxmn+W0hMEJZM8cZBMjQ7KRv9BgAeDImBsDTtacERURL67GQMOQzK/PlcwKxMndFjgmawv56Ul5+DZ2YOZBKMxqgog8gP0W2PAU4JFTfwgZYwuoU/A2dmlu9eUqtg/Cviw0OaTIjIM0ISD4N33BvW0c3uTtBfG3uj88W8pMrrsXDAWXv2oJatoxbQOCvIG31e9Ll4FNhPZWX4Jh9I+jTO3lBdASVgLHmbuedTQGGWaOBglP2og17B4G0X+vJYjLFlm8ZeeDinta2SN0CxQ92agtHV/pHHrCh4T3UBJr3cFCNczawYom3aswwnmpWEUKPWAsPyqYRiACW88NtLXx0uEBzP1h6B0oumIjoJNxGiJ1US3Q2PtSEM+nomePafo6Vr0q8flISJcpQqhNDJFOynpo6iZp90ZSDYkMssoBQ87m/xMTIc7gML/lIKdQ0BnAgRchA4VYRMR7WRZiPNOtuFFIHNkYBCdlTCov4mBD8Xg695ik9i8IjsAro24IYCmi4W0VvD1Jl9CG8WNOGv+o7GscY4CvpGOssaYoFNiNeQDYrCYqAVqu1ZReEWw/FSIglwj5Ezgy052iTN9tAulO3r9eNozraEX0k1fSqWXgRLG+xP3+6+62ozEUF4DYTvMZmnIJeneK42hyLov1H+nkct7XyORJZo+5wUAc5PlgEV7BGT6vJw4Ft+rzEmHQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 68bdb19c-1a58-4d13-d6ee-08da2ca01a01 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9186.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2022 00:58:57.2032 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mc9tDRJJJ6CrnoDPWY/43Hxce36dN+I/oMaXRJKDXHLVVpgQy2zHM4WK3QndEE3bWbigIPWZvCH6LLYQrk+zTg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4431 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some Endpoints controllers have DMA capabilities. This DMA controller has more efficiency then a general external DMA controller. And this DMA controller can bypass outbound memory address translation unit. The whole flow use standard DMA usage module 1. Using dma_request_channel() and filter function to find correct RX and TX Channel. if not exist, fallback to try allocate general DMA controller channel. 2. dmaengine_slave_config() config remote side physcial address. 3. using dmaengine_prep_slave_single() create transfer descriptor. 4. tx_submit(); 5. dma_async_issue_pending(); Signed-off-by: Frank Li Acked-by: Manivannan Sadhasivam --- Change from v9 to v10: - rewrite commit message Change from v4 to v9: - none Change from v3 to v4: - reverse Xmas tree order - local -> dma_local - change error message - IS_ERR -> IS_ERR_OR_NULL - check return value of dmaengine_slave_config() Change from v1 to v2: - none drivers/pci/endpoint/functions/pci-epf-test.c | 108 ++++++++++++++++-- 1 file changed, 98 insertions(+), 10 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 90d84d3bc868f..f26afd02f3a86 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -52,9 +52,11 @@ struct pci_epf_test { enum pci_barno test_reg_bar; size_t msix_table_offset; struct delayed_work cmd_handler; - struct dma_chan *dma_chan; + struct dma_chan *dma_chan_tx; + struct dma_chan *dma_chan_rx; struct completion transfer_complete; bool dma_supported; + bool dma_private; const struct pci_epc_features *epc_features; }; @@ -105,12 +107,15 @@ static void pci_epf_test_dma_callback(void *param) */ static int pci_epf_test_data_transfer(struct pci_epf_test *epf_test, dma_addr_t dma_dst, dma_addr_t dma_src, - size_t len) + size_t len, dma_addr_t dma_remote, + enum dma_transfer_direction dir) { + struct dma_chan *chan = (dir == DMA_DEV_TO_MEM) ? epf_test->dma_chan_tx : epf_test->dma_chan_rx; + dma_addr_t dma_local = (dir == DMA_MEM_TO_DEV) ? dma_src : dma_dst; enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; - struct dma_chan *chan = epf_test->dma_chan; struct pci_epf *epf = epf_test->epf; struct dma_async_tx_descriptor *tx; + struct dma_slave_config sconf = {}; struct device *dev = &epf->dev; dma_cookie_t cookie; int ret; @@ -120,7 +125,22 @@ static int pci_epf_test_data_transfer(struct pci_epf_test *epf_test, return -EINVAL; } - tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags); + if (epf_test->dma_private) { + sconf.direction = dir; + if (dir == DMA_MEM_TO_DEV) + sconf.dst_addr = dma_remote; + else + sconf.src_addr = dma_remote; + + if (dmaengine_slave_config(chan, &sconf)) { + dev_err(dev, "DMA slave config fail\n"); + return -EIO; + } + tx = dmaengine_prep_slave_single(chan, dma_local, len, dir, flags); + } else { + tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags); + } + if (!tx) { dev_err(dev, "Failed to prepare DMA memcpy\n"); return -EIO; @@ -148,6 +168,23 @@ static int pci_epf_test_data_transfer(struct pci_epf_test *epf_test, return 0; } +struct epf_dma_filter { + struct device *dev; + u32 dma_mask; +}; + +static bool epf_dma_filter_fn(struct dma_chan *chan, void *node) +{ + struct epf_dma_filter *filter = node; + struct dma_slave_caps caps; + + memset(&caps, 0, sizeof(caps)); + dma_get_slave_caps(chan, &caps); + + return chan->device->dev == filter->dev + && (filter->dma_mask & caps.directions); +} + /** * pci_epf_test_init_dma_chan() - Function to initialize EPF test DMA channel * @epf_test: the EPF test device that performs data transfer operation @@ -158,10 +195,44 @@ static int pci_epf_test_init_dma_chan(struct pci_epf_test *epf_test) { struct pci_epf *epf = epf_test->epf; struct device *dev = &epf->dev; + struct epf_dma_filter filter; struct dma_chan *dma_chan; dma_cap_mask_t mask; int ret; + filter.dev = epf->epc->dev.parent; + filter.dma_mask = BIT(DMA_DEV_TO_MEM); + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_chan = dma_request_channel(mask, epf_dma_filter_fn, &filter); + if (IS_ERR_OR_NULL(dma_chan)) { + dev_info(dev, "Failed to get private DMA channel. Falling back to generic one\n"); + goto fail_back_tx; + } + + epf_test->dma_chan_rx = dma_chan; + + filter.dma_mask = BIT(DMA_MEM_TO_DEV); + dma_chan = dma_request_channel(mask, epf_dma_filter_fn, &filter); + + if (IS_ERR(dma_chan)) { + dev_info(dev, "Failed to get private DMA channel. Falling back to generic one\n"); + goto fail_back_rx; + } + + epf_test->dma_chan_tx = dma_chan; + epf_test->dma_private = true; + + init_completion(&epf_test->transfer_complete); + + return 0; + +fail_back_rx: + dma_release_channel(epf_test->dma_chan_rx); + epf_test->dma_chan_tx = NULL; + +fail_back_tx: dma_cap_zero(mask); dma_cap_set(DMA_MEMCPY, mask); @@ -174,7 +245,7 @@ static int pci_epf_test_init_dma_chan(struct pci_epf_test *epf_test) } init_completion(&epf_test->transfer_complete); - epf_test->dma_chan = dma_chan; + epf_test->dma_chan_tx = epf_test->dma_chan_rx = dma_chan; return 0; } @@ -190,8 +261,17 @@ static void pci_epf_test_clean_dma_chan(struct pci_epf_test *epf_test) if (!epf_test->dma_supported) return; - dma_release_channel(epf_test->dma_chan); - epf_test->dma_chan = NULL; + dma_release_channel(epf_test->dma_chan_tx); + if (epf_test->dma_chan_tx == epf_test->dma_chan_rx) { + epf_test->dma_chan_tx = NULL; + epf_test->dma_chan_rx = NULL; + return; + } + + dma_release_channel(epf_test->dma_chan_rx); + epf_test->dma_chan_rx = NULL; + + return; } static void pci_epf_test_print_rate(const char *ops, u64 size, @@ -280,8 +360,14 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) goto err_map_addr; } + if (epf_test->dma_private) { + dev_err(dev, "Cannot transfer data using DMA\n"); + ret = -EINVAL; + goto err_map_addr; + } + ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr, - src_phys_addr, reg->size); + src_phys_addr, reg->size, 0, DMA_MEM_TO_MEM); if (ret) dev_err(dev, "Data transfer failed\n"); } else { @@ -363,7 +449,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) ktime_get_ts64(&start); ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr, - phys_addr, reg->size); + phys_addr, reg->size, + reg->src_addr, DMA_DEV_TO_MEM); if (ret) dev_err(dev, "Data transfer failed\n"); ktime_get_ts64(&end); @@ -453,8 +540,9 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) } ktime_get_ts64(&start); + ret = pci_epf_test_data_transfer(epf_test, phys_addr, - src_phys_addr, reg->size); + src_phys_addr, reg->size, reg->dst_addr, DMA_MEM_TO_DEV); if (ret) dev_err(dev, "Data transfer failed\n"); ktime_get_ts64(&end);