From patchwork Tue May 17 12:50:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7A4CC433F5 for ; Tue, 17 May 2022 12:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346459AbiEQMvv (ORCPT ); Tue, 17 May 2022 08:51:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346417AbiEQMvr (ORCPT ); Tue, 17 May 2022 08:51:47 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 48CF23F889; Tue, 17 May 2022 05:51:39 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id B184EBD4; Tue, 17 May 2022 15:52:35 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru B184EBD4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791955; bh=HvFRjLfRZVpB1a2dJ+Y3tW+LbZlq0RtxiS2ht743LVQ=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=GZINoVA2cAE0s74DZOslmcgg+RVjJqa0Yu+dH52V7n5FiZ88SUN2JtUEUhAD00Oht b2KQdUEQqH/1hTaA282qN7kIWiZ/BAPSY1vPa46TKMVBpkrxHKgae52gikT9uVwfFt yPRxGka2qPU2fq31JQQvnVVJKNZEASyEeDWkHEPo= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:38 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 03/13] PCI: dwc: Add unroll iATU space support to the regions disable method Date: Tue, 17 May 2022 15:50:48 +0300 Message-ID: <20220517125058.18488-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The dw_pcie_disable_atu() method was introduced in the commit f8aed6ec624f ("PCI: dwc: designware: Add EP mode support"). Since then it hasn't changed at all. For all that time the method has supported the viewport version of the iATU CSRs only. Basically it works for the DW PCIe IP-cores older than v4.80a since the newer controllers are equipped with the unrolled iATU/eDMA space. It means the methods using it like pci_epc_ops.clear_bar and pci_epc_ops.unmap_addr callbacks just don't work correctly for the DW PCIe controllers with unrolled iATU CSRs. The same concerns the dw_pcie_setup_rc() method, which disables the outbound iATU entries before re-initializing them. So in order to fix the problems denoted above let's convert the dw_pcie_disable_atu() method to disabling the iATU inbound and outbound regions in the unrolled iATU CSRs in case the DW PCIe controller has been synthesized with the ones support. The former semantics will be remained for the controller having iATU mapped over the viewport. Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- Changelog v3: - Convert region variable type to u32 in order to fix the implicit type conversion peculiarity. (@kbot) --- drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d92c8a25094f..84fef21efdbc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -491,7 +491,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, void dw_pcie_disable_atu(struct dw_pcie *pci, int index, enum dw_pcie_region_type type) { - int region; + u32 region; switch (type) { case DW_PCIE_REGION_INBOUND: @@ -504,8 +504,18 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index, return; } - dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); + if (pci->iatu_unroll_enabled) { + if (region == PCIE_ATU_REGION_INBOUND) { + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + ~(u32)PCIE_ATU_ENABLE); + } else { + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + ~(u32)PCIE_ATU_ENABLE); + } + } else { + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); + } } int dw_pcie_wait_for_link(struct dw_pcie *pci)