From patchwork Fri Jun 10 08:25:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12876705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B3F5CCA47E for ; Fri, 10 Jun 2022 08:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344049AbiFJI3W (ORCPT ); Fri, 10 Jun 2022 04:29:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347604AbiFJI1n (ORCPT ); Fri, 10 Jun 2022 04:27:43 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E4CDD267B; Fri, 10 Jun 2022 01:25:53 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 3C855BD6; Fri, 10 Jun 2022 11:26:33 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 3C855BD6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1654849593; bh=3qGTdt7z7PgMIeLrOUnz8BGjA4aE8NJd1KjGC5/ncCc=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=KCOgRQzkZGhN41Hq8EDeHQFdkm/6XYmFTv2D9WtplV/U0jBYIBdOmnQBYhiRCvWfJ SKP8+GDUiA8R8AJsrJpgl7TWNDIKPJZjoM9RoFkGm9jgn74w9GHd09HNYHlL2aQJEP pv+Vzd6pU0NrvTiHCVVxNnPtVFG/KLLqftekaFVo= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 10 Jun 2022 11:25:40 +0300 From: Serge Semin To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , =?utf-8?q?Krzysztof_Wilcz?= =?utf-8?q?y=C5=84ski?= , Vidya Sagar , Thierry Reding CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , , Subject: [PATCH v4 06/18] PCI: dwc: Enable CDM-check independently from the num_lanes value Date: Fri, 10 Jun 2022 11:25:22 +0300 Message-ID: <20220610082535.12802-7-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru> References: <20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently the embedded CDM IOs consistency check-engine is enabled only if the num_lanes field of dw_pcie structure is set to non-zero value. It's definitely wrong since the CDM checking has nothing to do with the PCIe lanes settings, while that feature will be left disabled for the platforms which expect it being enabled and prefer keeping the default lanes setup. Let's fix that by enabling the CDM-check feature before the num_lanes parameter is handled. Fixes: 07f123def73e ("PCI: dwc: Add support to enable CDM register check") Signed-off-by: Serge Semin Reviewed-by: Vidya Sagar Reviewed-by: Rob Herring --- Changelog v4: - This is a new patch created on v4 lap of the series. --- drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 347251bf87d0..5848cc520b52 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -740,6 +740,13 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + if (of_property_read_bool(np, "snps,enable-cdm-check")) { + val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); + val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | + PCIE_PL_CHK_REG_CHK_REG_START; + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); + } + of_property_read_u32(np, "num-lanes", &pci->num_lanes); if (!pci->num_lanes) { dev_dbg(pci->dev, "Using h/w default number of lanes\n"); @@ -786,11 +793,4 @@ void dw_pcie_setup(struct dw_pcie *pci) break; } dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); - - if (of_property_read_bool(np, "snps,enable-cdm-check")) { - val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); - val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | - PCIE_PL_CHK_REG_CHK_REG_START; - dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); - } }